1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <lsc25_e_core.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "LSC25 E-core must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "LSC25 E-core supports only AArch64. Compile with " \ 22 "CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "LSC25 E-core needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue lsc25_e_core 30 31cpu_reset_func_start lsc25_e_core 32 /* ---------------------------------------------------- 33 * Disable speculative loads 34 * ---------------------------------------------------- 35 */ 36 msr SSBS, xzr 37 enable_mpmm 38cpu_reset_func_end lsc25_e_core 39 40 /* ---------------------------------------------------- 41 * HW will do the cache maintenance while powering down 42 * ---------------------------------------------------- 43 */ 44func lsc25_e_core_core_pwr_dwn 45 /* --------------------------------------------------- 46 * Flip CPU power down bit in power control register. 47 * It will be set on powerdown and cleared on wakeup 48 * --------------------------------------------------- 49 */ 50 sysreg_bit_toggle LSC25_E_CORE_IMP_CPUPWRCTLR_EL1, \ 51 LSC25_E_CORE_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 52 isb 53 signal_pabandon_handled 54 ret 55endfunc lsc25_e_core_core_pwr_dwn 56 57 /* --------------------------------------------- 58 * This function provides LSC25 E-Core specific 59 * register information for crash reporting. 60 * It needs to return with x6 pointing to 61 * a list of register names in ascii and 62 * x8 - x15 having values of registers to be 63 * reported. 64 * --------------------------------------------- 65 */ 66.section .rodata.lsc25_e_core_regs, "aS" 67lsc25_e_core_regs: /* The ASCII list of register names to be reported */ 68 .asciz "imp_cpuectlr_el1", "" 69 70func lsc25_e_core_cpu_reg_dump 71 adr x6, lsc25_e_core_regs 72 mrs x8, LSC25_E_CORE_IMP_CPUECTLR_EL1 73 ret 74endfunc lsc25_e_core_cpu_reg_dump 75 76declare_cpu_ops lsc25_e_core, LSC25_E_CORE_MIDR, \ 77 lsc25_e_core_reset_func, \ 78 lsc25_e_core_core_pwr_dwn 79