1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <generic.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14cpu_reset_prologue generic 15 16func generic_core_pwr_dwn 17 mov x18, x30 18 19 /* --------------------------------------------- 20 * Flush L1 caches. 21 * --------------------------------------------- 22 */ 23 mov x0, #DCCISW 24 bl dcsw_op_level1 25 26 ret x18 27endfunc generic_core_pwr_dwn 28 29func generic_cluster_pwr_dwn 30 mov x18, x30 31 32 /* --------------------------------------------- 33 * Flush L1 caches. 34 * --------------------------------------------- 35 */ 36 mov x0, #DCCISW 37 bl dcsw_op_level1 38 39 /* --------------------------------------------- 40 * Disable the optional ACP. 41 * --------------------------------------------- 42 */ 43 bl plat_disable_acp 44 45 /* --------------------------------------------- 46 * Flush L2 caches. 47 * --------------------------------------------- 48 */ 49 mov x0, #DCCISW 50 bl dcsw_op_level2 51 52 ret x18 53 54endfunc generic_cluster_pwr_dwn 55 56/* --------------------------------------------- 57 * Unimplemented functions. 58 * --------------------------------------------- 59 */ 60.equ generic_cpu_reg_dump, 0 61 62cpu_reset_func_start generic 63cpu_reset_func_end generic 64 65declare_cpu_ops generic, AARCH64_GENERIC_MIDR, \ 66 generic_reset_func, \ 67 generic_core_pwr_dwn, \ 68 generic_cluster_pwr_dwn 69