1/* 2 * Copyright (c) 2022-2024, Google LLC. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <cortex_x1.h> 9#include <cpu_macros.S> 10#include "wa_cve_2022_23960_bhb_vector.S" 11 12/* Hardware handled coherency */ 13#if HW_ASSISTED_COHERENCY == 0 14#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled" 15#endif 16 17/* 64-bit only core */ 18#if CTX_INCLUDE_AARCH32_REGS == 1 19#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20#endif 21 22#if WORKAROUND_CVE_2022_23960 23 wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1 24#endif /* WORKAROUND_CVE_2022_23960 */ 25 26cpu_reset_prologue cortex_x1 27 28/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 29workaround_reset_start cortex_x1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 30 sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(46) 31workaround_reset_end cortex_x1, CVE(2024, 5660) 32 33check_erratum_ls cortex_x1, CVE(2024, 5660), CPU_REV(1, 2) 34 35workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305 36 sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1) 37workaround_reset_end cortex_x1, ERRATUM(1688305) 38 39check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0) 40 41workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534 42 sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2) 43workaround_reset_end cortex_x1, ERRATUM(1821534) 44 45check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0) 46 47workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429 48 sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53) 49workaround_reset_end cortex_x1, ERRATUM(1827429) 50 51check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0) 52 53check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 54 55workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 56#if IMAGE_BL31 57 /* 58 * The Cortex-X1 generic vectors are overridden to apply errata 59 * mitigation on exception entry from lower ELs. 60 */ 61 override_vector_table wa_cve_vbar_cortex_x1 62#endif /* IMAGE_BL31 */ 63workaround_reset_end cortex_x1, CVE(2022, 23960) 64 65cpu_reset_func_start cortex_x1 66cpu_reset_func_end cortex_x1 67 68 /* --------------------------------------------- 69 * HW will do the cache maintenance while powering down 70 * --------------------------------------------- 71 */ 72func cortex_x1_core_pwr_dwn 73 sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK 74 isb 75 ret 76endfunc cortex_x1_core_pwr_dwn 77 78 /* --------------------------------------------- 79 * This function provides Cortex X1 specific 80 * register information for crash reporting. 81 * It needs to return with x6 pointing to 82 * a list of register names in ascii and 83 * x8 - x15 having values of registers to be 84 * reported. 85 * --------------------------------------------- 86 */ 87.section .rodata.cortex_x1_regs, "aS" 88cortex_x1_regs: /* The ascii list of register names to be reported */ 89 .asciz "cpuectlr_el1", "" 90 91func cortex_x1_cpu_reg_dump 92 adr x6, cortex_x1_regs 93 mrs x8, CORTEX_X1_CPUECTLR_EL1 94 ret 95endfunc cortex_x1_cpu_reg_dump 96 97declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \ 98 cortex_x1_reset_func, \ 99 cortex_x1_core_pwr_dwn 100