1/* 2 * Copyright (c) 2019, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <cortex_a76ae.h> 9#include <cpu_macros.S> 10 11 /* --------------------------------------------- 12 * HW will do the cache maintenance while powering down 13 * --------------------------------------------- 14 */ 15func cortex_a76ae_core_pwr_dwn 16 /* --------------------------------------------- 17 * Enable CPU power down bit in power control register 18 * --------------------------------------------- 19 */ 20 mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1 21 orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK 22 msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0 23 isb 24 ret 25endfunc cortex_a76ae_core_pwr_dwn 26 27#if REPORT_ERRATA 28/* 29 * Errata printing function for Cortex-A76AE. Must follow AAPCS. 30 */ 31func cortex_a76ae_errata_report 32 ret 33endfunc cortex_a76ae_errata_report 34#endif /* REPORT_ERRATA */ 35 36 /* --------------------------------------------- 37 * This function provides cortex_a76ae specific 38 * register information for crash reporting. 39 * It needs to return with x6 pointing to 40 * a list of register names in ascii and 41 * x8 - x15 having values of registers to be 42 * reported. 43 * --------------------------------------------- 44 */ 45.section .rodata.cortex_a76ae_regs, "aS" 46cortex_a76ae_regs: /* The ASCII list of register names to be reported */ 47 .asciz "cpuectlr_el1", "" 48 49func cortex_a76ae_cpu_reg_dump 50 adr x6, cortex_a76ae_regs 51 mrs x8, CORTEX_A76AE_CPUECTLR_EL1 52 ret 53endfunc cortex_a76ae_cpu_reg_dump 54 55declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, CPU_NO_RESET_FUNC, \ 56 cortex_a76ae_core_pwr_dwn 57