1/* 2 * Copyright (c) 2019, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <cortex_a76ae.h> 9#include <cpu_macros.S> 10 11/* Hardware handled coherency */ 12#if HW_ASSISTED_COHERENCY == 0 13#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" 14#endif 15 16 /* --------------------------------------------- 17 * HW will do the cache maintenance while powering down 18 * --------------------------------------------- 19 */ 20func cortex_a76ae_core_pwr_dwn 21 /* --------------------------------------------- 22 * Enable CPU power down bit in power control register 23 * --------------------------------------------- 24 */ 25 mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1 26 orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK 27 msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0 28 isb 29 ret 30endfunc cortex_a76ae_core_pwr_dwn 31 32#if REPORT_ERRATA 33/* 34 * Errata printing function for Cortex-A76AE. Must follow AAPCS. 35 */ 36func cortex_a76ae_errata_report 37 ret 38endfunc cortex_a76ae_errata_report 39#endif /* REPORT_ERRATA */ 40 41 /* --------------------------------------------- 42 * This function provides cortex_a76ae specific 43 * register information for crash reporting. 44 * It needs to return with x6 pointing to 45 * a list of register names in ascii and 46 * x8 - x15 having values of registers to be 47 * reported. 48 * --------------------------------------------- 49 */ 50.section .rodata.cortex_a76ae_regs, "aS" 51cortex_a76ae_regs: /* The ASCII list of register names to be reported */ 52 .asciz "cpuectlr_el1", "" 53 54func cortex_a76ae_cpu_reg_dump 55 adr x6, cortex_a76ae_regs 56 mrs x8, CORTEX_A76AE_CPUECTLR_EL1 57 ret 58endfunc cortex_a76ae_cpu_reg_dump 59 60declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, CPU_NO_RESET_FUNC, \ 61 cortex_a76ae_core_pwr_dwn 62