1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a73_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a73_disable_smp 30 mrs x0, CORTEX_A73_CPUECTLR_EL1 31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 32 msr CORTEX_A73_CPUECTLR_EL1, x0 33 isb 34 dsb sy 35 ret 36endfunc cortex_a73_disable_smp 37 38 /* --------------------------------------------------- 39 * Errata Workaround for Cortex A73 Errata #855423. 40 * This applies only to revision <= r0p1 of Cortex A73. 41 * Inputs: 42 * x0: variant[4:7] and revision[0:3] of current cpu. 43 * Shall clobber: x0-x17 44 * --------------------------------------------------- 45 */ 46func errata_a73_855423_wa 47 /* 48 * Compare x0 against revision r0p1 49 */ 50 mov x17, x30 51 bl check_errata_855423 52 cbz x0, 1f 53 mrs x1, CORTEX_A73_IMP_DEF_REG2 54 orr x1, x1, #(1 << 7) 55 msr CORTEX_A73_IMP_DEF_REG2, x1 56 isb 571: 58 ret x17 59endfunc errata_a73_855423_wa 60 61func check_errata_855423 62 mov x1, #0x01 63 b cpu_rev_var_ls 64endfunc check_errata_855423 65 66 /* ------------------------------------------------- 67 * The CPU Ops reset function for Cortex-A73. 68 * ------------------------------------------------- 69 */ 70 71func cortex_a73_reset_func 72 mov x19, x30 73 bl cpu_get_rev_var 74 75#if ERRATA_A73_855423 76 bl errata_a73_855423_wa 77#endif 78 79#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 80 cpu_check_csv2 x0, 1f 81 adr x0, wa_cve_2017_5715_bpiall_vbar 82 msr vbar_el3, x0 83 /* isb will be performed before returning from this function */ 841: 85#endif 86 87#if WORKAROUND_CVE_2018_3639 88 mrs x0, CORTEX_A73_IMP_DEF_REG1 89 orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 90 msr CORTEX_A73_IMP_DEF_REG1, x0 91 isb 92#endif 93 94 /* --------------------------------------------- 95 * Enable the SMP bit. 96 * Clobbers : x0 97 * --------------------------------------------- 98 */ 99 mrs x0, CORTEX_A73_CPUECTLR_EL1 100 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 101 msr CORTEX_A73_CPUECTLR_EL1, x0 102 isb 103 ret x19 104endfunc cortex_a73_reset_func 105 106func cortex_a73_core_pwr_dwn 107 mov x18, x30 108 109 /* --------------------------------------------- 110 * Turn off caches. 111 * --------------------------------------------- 112 */ 113 bl cortex_a73_disable_dcache 114 115 /* --------------------------------------------- 116 * Flush L1 caches. 117 * --------------------------------------------- 118 */ 119 mov x0, #DCCISW 120 bl dcsw_op_level1 121 122 /* --------------------------------------------- 123 * Come out of intra cluster coherency 124 * --------------------------------------------- 125 */ 126 mov x30, x18 127 b cortex_a73_disable_smp 128endfunc cortex_a73_core_pwr_dwn 129 130func cortex_a73_cluster_pwr_dwn 131 mov x18, x30 132 133 /* --------------------------------------------- 134 * Turn off caches. 135 * --------------------------------------------- 136 */ 137 bl cortex_a73_disable_dcache 138 139 /* --------------------------------------------- 140 * Flush L1 caches. 141 * --------------------------------------------- 142 */ 143 mov x0, #DCCISW 144 bl dcsw_op_level1 145 146 /* --------------------------------------------- 147 * Disable the optional ACP. 148 * --------------------------------------------- 149 */ 150 bl plat_disable_acp 151 152 /* --------------------------------------------- 153 * Flush L2 caches. 154 * --------------------------------------------- 155 */ 156 mov x0, #DCCISW 157 bl dcsw_op_level2 158 159 /* --------------------------------------------- 160 * Come out of intra cluster coherency 161 * --------------------------------------------- 162 */ 163 mov x30, x18 164 b cortex_a73_disable_smp 165endfunc cortex_a73_cluster_pwr_dwn 166 167func check_errata_cve_2017_5715 168 cpu_check_csv2 x0, 1f 169#if WORKAROUND_CVE_2017_5715 170 mov x0, #ERRATA_APPLIES 171#else 172 mov x0, #ERRATA_MISSING 173#endif 174 ret 1751: 176 mov x0, #ERRATA_NOT_APPLIES 177 ret 178endfunc check_errata_cve_2017_5715 179 180func check_errata_cve_2018_3639 181#if WORKAROUND_CVE_2018_3639 182 mov x0, #ERRATA_APPLIES 183#else 184 mov x0, #ERRATA_MISSING 185#endif 186 ret 187endfunc check_errata_cve_2018_3639 188 189#if REPORT_ERRATA 190/* 191 * Errata printing function for Cortex A75. Must follow AAPCS. 192 */ 193func cortex_a73_errata_report 194 stp x8, x30, [sp, #-16]! 195 196 bl cpu_get_rev_var 197 mov x8, x0 198 199 /* 200 * Report all errata. The revision-variant information is passed to 201 * checking functions of each errata. 202 */ 203 report_errata ERRATA_A73_855423, cortex_a73, 855423 204 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715 205 report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639 206 207 ldp x8, x30, [sp], #16 208 ret 209endfunc cortex_a73_errata_report 210#endif 211 212 /* --------------------------------------------- 213 * This function provides cortex_a73 specific 214 * register information for crash reporting. 215 * It needs to return with x6 pointing to 216 * a list of register names in ascii and 217 * x8 - x15 having values of registers to be 218 * reported. 219 * --------------------------------------------- 220 */ 221.section .rodata.cortex_a73_regs, "aS" 222cortex_a73_regs: /* The ascii list of register names to be reported */ 223 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 224 225func cortex_a73_cpu_reg_dump 226 adr x6, cortex_a73_regs 227 mrs x8, CORTEX_A73_CPUECTLR_EL1 228 mrs x9, CORTEX_A73_L2MERRSR_EL1 229 ret 230endfunc cortex_a73_cpu_reg_dump 231 232declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 233 cortex_a73_reset_func, \ 234 check_errata_cve_2017_5715, \ 235 CPU_NO_EXTRA2_FUNC, \ 236 cortex_a73_core_pwr_dwn, \ 237 cortex_a73_cluster_pwr_dwn 238