1/* 2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13cpu_reset_prologue cortex_a73 14 15 /* --------------------------------------------- 16 * Disable intra-cluster coherency 17 * --------------------------------------------- 18 */ 19func cortex_a73_disable_smp 20 sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 21 isb 22 dsb sy 23 ret 24endfunc cortex_a73_disable_smp 25 26/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 27add_erratum_entry cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 28 29check_erratum_chosen cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 30 31workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 32 sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12) 33workaround_reset_end cortex_a73, ERRATUM(852427) 34 35check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) 36 37workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 38 sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7) 39workaround_reset_end cortex_a73, ERRATUM(855423) 40 41check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) 42 43workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 44#if IMAGE_BL31 45 override_vector_table wa_cve_2017_5715_bpiall_vbar 46#endif /* IMAGE_BL31 */ 47workaround_reset_end cortex_a73, CVE(2017, 5715) 48 49/* r1p0 implements FEAT_CSV2 */ 50check_erratum_ls cortex_a73, CVE(2017, 5715), CPU_REV(1, 0) 51 52workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 53 sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 54workaround_reset_end cortex_a73, CVE(2018, 3639) 55 56check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 57 58workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 59#if IMAGE_BL31 60 /* Skip installing vector table again for CVE_2022_23960 */ 61 adr x0, wa_cve_2017_5715_bpiall_vbar 62 mrs x1, vbar_el3 63 64 cmp x0, x1 65 b.eq 1f 66 msr vbar_el3, x0 671: 68#endif /* IMAGE_BL31 */ 69workaround_reset_end cortex_a73, CVE(2022, 23960) 70 71check_erratum_custom_start cortex_a73, CVE(2022, 23960) 72#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 73 cpu_check_csv2 x0, 1f 74 mov x0, #ERRATA_APPLIES 75 ret 76 1: 77#if WORKAROUND_CVE_2022_23960 78 mov x0, #ERRATA_APPLIES 79#else 80 mov x0, #ERRATA_MISSING 81#endif /* WORKAROUND_CVE_2022_23960 */ 82 ret 83#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 84 mov x0, #ERRATA_MISSING 85 ret 86check_erratum_custom_end cortex_a73, CVE(2022, 23960) 87 88 /* ------------------------------------------------- 89 * The CPU Ops reset function for Cortex-A73. 90 * ------------------------------------------------- 91 */ 92 93cpu_reset_func_start cortex_a73 94 /* --------------------------------------------- 95 * Enable the SMP bit. 96 * Clobbers : x0 97 * --------------------------------------------- 98 */ 99 sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 100cpu_reset_func_end cortex_a73 101 102func cortex_a73_core_pwr_dwn 103 mov x18, x30 104 105 /* --------------------------------------------- 106 * Flush L1 caches. 107 * --------------------------------------------- 108 */ 109 mov x0, #DCCISW 110 bl dcsw_op_level1 111 112 /* --------------------------------------------- 113 * Come out of intra cluster coherency 114 * --------------------------------------------- 115 */ 116 mov x30, x18 117 b cortex_a73_disable_smp 118endfunc cortex_a73_core_pwr_dwn 119 120func cortex_a73_cluster_pwr_dwn 121 mov x18, x30 122 123 /* --------------------------------------------- 124 * Flush L1 caches. 125 * --------------------------------------------- 126 */ 127 mov x0, #DCCISW 128 bl dcsw_op_level1 129 130 /* --------------------------------------------- 131 * Disable the optional ACP. 132 * --------------------------------------------- 133 */ 134 bl plat_disable_acp 135 136 /* --------------------------------------------- 137 * Flush L2 caches. 138 * --------------------------------------------- 139 */ 140 mov x0, #DCCISW 141 bl dcsw_op_level2 142 143 /* --------------------------------------------- 144 * Come out of intra cluster coherency 145 * --------------------------------------------- 146 */ 147 mov x30, x18 148 b cortex_a73_disable_smp 149endfunc cortex_a73_cluster_pwr_dwn 150 151 /* --------------------------------------------- 152 * This function provides cortex_a73 specific 153 * register information for crash reporting. 154 * It needs to return with x6 pointing to 155 * a list of register names in ascii and 156 * x8 - x15 having values of registers to be 157 * reported. 158 * --------------------------------------------- 159 */ 160.section .rodata.cortex_a73_regs, "aS" 161cortex_a73_regs: /* The ascii list of register names to be reported */ 162 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 163 164func cortex_a73_cpu_reg_dump 165 adr x6, cortex_a73_regs 166 mrs x8, CORTEX_A73_CPUECTLR_EL1 167 mrs x9, CORTEX_A73_L2MERRSR_EL1 168 ret 169endfunc cortex_a73_cpu_reg_dump 170 171declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \ 172 cortex_a73_reset_func, \ 173 cortex_a73_core_pwr_dwn, \ 174 cortex_a73_cluster_pwr_dwn 175