1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <bl_common.h> 33#include <cortex_a73.h> 34#include <cpu_macros.S> 35#include <plat_macros.S> 36 37 /* --------------------------------------------- 38 * Disable L1 data cache 39 * --------------------------------------------- 40 */ 41func cortex_a73_disable_dcache 42 mrs x1, sctlr_el3 43 bic x1, x1, #SCTLR_C_BIT 44 msr sctlr_el3, x1 45 isb 46 ret 47endfunc cortex_a73_disable_dcache 48 49 /* --------------------------------------------- 50 * Disable intra-cluster coherency 51 * --------------------------------------------- 52 */ 53func cortex_a73_disable_smp 54 mrs x0, CORTEX_A73_CPUECTLR_EL1 55 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 56 msr CORTEX_A73_CPUECTLR_EL1, x0 57 isb 58 dsb sy 59 ret 60endfunc cortex_a73_disable_smp 61 62func cortex_a73_reset_func 63 /* --------------------------------------------- 64 * Enable the SMP bit. 65 * Clobbers : x0 66 * --------------------------------------------- 67 */ 68 mrs x0, CORTEX_A73_CPUECTLR_EL1 69 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 70 msr CORTEX_A73_CPUECTLR_EL1, x0 71 isb 72 ret 73endfunc cortex_a73_reset_func 74 75func cortex_a73_core_pwr_dwn 76 mov x18, x30 77 78 /* --------------------------------------------- 79 * Turn off caches. 80 * --------------------------------------------- 81 */ 82 bl cortex_a73_disable_dcache 83 84 /* --------------------------------------------- 85 * Flush L1 caches. 86 * --------------------------------------------- 87 */ 88 mov x0, #DCCISW 89 bl dcsw_op_level1 90 91 /* --------------------------------------------- 92 * Come out of intra cluster coherency 93 * --------------------------------------------- 94 */ 95 mov x30, x18 96 b cortex_a73_disable_smp 97endfunc cortex_a73_core_pwr_dwn 98 99func cortex_a73_cluster_pwr_dwn 100 mov x18, x30 101 102 /* --------------------------------------------- 103 * Turn off caches. 104 * --------------------------------------------- 105 */ 106 bl cortex_a73_disable_dcache 107 108 /* --------------------------------------------- 109 * Flush L1 caches. 110 * --------------------------------------------- 111 */ 112 mov x0, #DCCISW 113 bl dcsw_op_level1 114 115 /* --------------------------------------------- 116 * Disable the optional ACP. 117 * --------------------------------------------- 118 */ 119 bl plat_disable_acp 120 121 /* --------------------------------------------- 122 * Flush L2 caches. 123 * --------------------------------------------- 124 */ 125 mov x0, #DCCISW 126 bl dcsw_op_level2 127 128 /* --------------------------------------------- 129 * Come out of intra cluster coherency 130 * --------------------------------------------- 131 */ 132 mov x30, x18 133 b cortex_a73_disable_smp 134endfunc cortex_a73_cluster_pwr_dwn 135 136 /* --------------------------------------------- 137 * This function provides cortex_a73 specific 138 * register information for crash reporting. 139 * It needs to return with x6 pointing to 140 * a list of register names in ascii and 141 * x8 - x15 having values of registers to be 142 * reported. 143 * --------------------------------------------- 144 */ 145.section .rodata.cortex_a73_regs, "aS" 146cortex_a73_regs: /* The ascii list of register names to be reported */ 147 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 148 149func cortex_a73_cpu_reg_dump 150 adr x6, cortex_a73_regs 151 mrs x8, CORTEX_A73_CPUECTLR_EL1 152 mrs x9, CORTEX_A73_L2MERRSR_EL1 153 ret 154endfunc cortex_a73_cpu_reg_dump 155 156declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \ 157 cortex_a73_reset_func, \ 158 cortex_a73_core_pwr_dwn, \ 159 cortex_a73_cluster_pwr_dwn 160