1/* 2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13cpu_reset_prologue cortex_a73 14 15 /* --------------------------------------------- 16 * Disable L1 data cache 17 * --------------------------------------------- 18 */ 19func cortex_a73_disable_dcache 20 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT 21 isb 22 ret 23endfunc cortex_a73_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a73_disable_smp 30 sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 31 isb 32 dsb sy 33 ret 34endfunc cortex_a73_disable_smp 35 36func check_smccc_arch_workaround_3 37 mov x0, #ERRATA_APPLIES 38 ret 39endfunc check_smccc_arch_workaround_3 40 41workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 42 sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12) 43workaround_reset_end cortex_a73, ERRATUM(852427) 44 45check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) 46 47workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 48 sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7) 49workaround_reset_end cortex_a73, ERRATUM(855423) 50 51check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) 52 53workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 54#if IMAGE_BL31 55 override_vector_table wa_cve_2017_5715_bpiall_vbar 56#endif /* IMAGE_BL31 */ 57workaround_reset_end cortex_a73, CVE(2017, 5715) 58 59check_erratum_custom_start cortex_a73, CVE(2017, 5715) 60 cpu_check_csv2 x0, 1f 61#if WORKAROUND_CVE_2017_5715 62 mov x0, #ERRATA_APPLIES 63#else 64 mov x0, #ERRATA_MISSING 65#endif 66 ret 671: 68 mov x0, #ERRATA_NOT_APPLIES 69 ret 70check_erratum_custom_end cortex_a73, CVE(2017, 5715) 71 72workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 73 sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 74workaround_reset_end cortex_a73, CVE(2018, 3639) 75 76check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 77 78workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 79#if IMAGE_BL31 80 /* Skip installing vector table again for CVE_2022_23960 */ 81 adr x0, wa_cve_2017_5715_bpiall_vbar 82 mrs x1, vbar_el3 83 84 cmp x0, x1 85 b.eq 1f 86 msr vbar_el3, x0 871: 88#endif /* IMAGE_BL31 */ 89workaround_reset_end cortex_a73, CVE(2022, 23960) 90 91check_erratum_custom_start cortex_a73, CVE(2022, 23960) 92#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 93 cpu_check_csv2 x0, 1f 94 mov x0, #ERRATA_APPLIES 95 ret 96 1: 97#if WORKAROUND_CVE_2022_23960 98 mov x0, #ERRATA_APPLIES 99#else 100 mov x0, #ERRATA_MISSING 101#endif /* WORKAROUND_CVE_2022_23960 */ 102 ret 103#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 104 mov x0, #ERRATA_MISSING 105 ret 106check_erratum_custom_end cortex_a73, CVE(2022, 23960) 107 108 /* ------------------------------------------------- 109 * The CPU Ops reset function for Cortex-A73. 110 * ------------------------------------------------- 111 */ 112 113cpu_reset_func_start cortex_a73 114 /* --------------------------------------------- 115 * Enable the SMP bit. 116 * Clobbers : x0 117 * --------------------------------------------- 118 */ 119 sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 120cpu_reset_func_end cortex_a73 121 122func cortex_a73_core_pwr_dwn 123 mov x18, x30 124 125 /* --------------------------------------------- 126 * Turn off caches. 127 * --------------------------------------------- 128 */ 129 bl cortex_a73_disable_dcache 130 131 /* --------------------------------------------- 132 * Flush L1 caches. 133 * --------------------------------------------- 134 */ 135 mov x0, #DCCISW 136 bl dcsw_op_level1 137 138 /* --------------------------------------------- 139 * Come out of intra cluster coherency 140 * --------------------------------------------- 141 */ 142 mov x30, x18 143 b cortex_a73_disable_smp 144endfunc cortex_a73_core_pwr_dwn 145 146func cortex_a73_cluster_pwr_dwn 147 mov x18, x30 148 149 /* --------------------------------------------- 150 * Turn off caches. 151 * --------------------------------------------- 152 */ 153 bl cortex_a73_disable_dcache 154 155 /* --------------------------------------------- 156 * Flush L1 caches. 157 * --------------------------------------------- 158 */ 159 mov x0, #DCCISW 160 bl dcsw_op_level1 161 162 /* --------------------------------------------- 163 * Disable the optional ACP. 164 * --------------------------------------------- 165 */ 166 bl plat_disable_acp 167 168 /* --------------------------------------------- 169 * Flush L2 caches. 170 * --------------------------------------------- 171 */ 172 mov x0, #DCCISW 173 bl dcsw_op_level2 174 175 /* --------------------------------------------- 176 * Come out of intra cluster coherency 177 * --------------------------------------------- 178 */ 179 mov x30, x18 180 b cortex_a73_disable_smp 181endfunc cortex_a73_cluster_pwr_dwn 182 183 /* --------------------------------------------- 184 * This function provides cortex_a73 specific 185 * register information for crash reporting. 186 * It needs to return with x6 pointing to 187 * a list of register names in ascii and 188 * x8 - x15 having values of registers to be 189 * reported. 190 * --------------------------------------------- 191 */ 192.section .rodata.cortex_a73_regs, "aS" 193cortex_a73_regs: /* The ascii list of register names to be reported */ 194 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 195 196func cortex_a73_cpu_reg_dump 197 adr x6, cortex_a73_regs 198 mrs x8, CORTEX_A73_CPUECTLR_EL1 199 mrs x9, CORTEX_A73_L2MERRSR_EL1 200 ret 201endfunc cortex_a73_cpu_reg_dump 202 203declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 204 cortex_a73_reset_func, \ 205 check_erratum_cortex_a73_5715, \ 206 CPU_NO_EXTRA2_FUNC, \ 207 check_smccc_arch_workaround_3, \ 208 cortex_a73_core_pwr_dwn, \ 209 cortex_a73_cluster_pwr_dwn 210