1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_a720 27 28.global check_erratum_cortex_a720_3699561 29 30#if WORKAROUND_CVE_2022_23960 31 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 32#endif /* WORKAROUND_CVE_2022_23960 */ 33 34workaround_reset_start cortex_a720, ERRATUM(2792132), ERRATA_A720_2792132 35 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26) 36workaround_reset_end cortex_a720, ERRATUM(2792132) 37 38check_erratum_ls cortex_a720, ERRATUM(2792132), CPU_REV(0, 1) 39 40workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092 41 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 42workaround_reset_end cortex_a720, ERRATUM(2844092) 43 44check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1) 45 46workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952 47 errata_dsu_2900952_wa_apply 48workaround_reset_end cortex_a720, ERRATUM(2900952) 49 50check_erratum_custom_start cortex_a720, ERRATUM(2900952) 51 check_errata_dsu_2900952_applies 52 ret 53check_erratum_custom_end cortex_a720, ERRATUM(2900952) 54 55workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 56/* Erratum 2926083 workaround is required only if SPE is enabled */ 57#if ENABLE_SPE_FOR_NS != 0 58 /* Check if Static profiling extension is implemented or present. */ 59 mrs x1, id_aa64dfr0_el1 60 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 61 cbz x0, 1f 62 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 63 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57) 64 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58) 651: 66#endif 67workaround_reset_end cortex_a720, ERRATUM(2926083) 68 69check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) 70 71workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 72 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 73workaround_reset_end cortex_a720, ERRATUM(2940794) 74 75check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 76 77workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 78#if IMAGE_BL31 79 /* 80 * The Cortex A720 generic vectors are overridden to apply errata 81 * mitigation on exception entry from lower ELs. 82 */ 83 override_vector_table wa_cve_vbar_cortex_a720 84#endif /* IMAGE_BL31 */ 85workaround_reset_end cortex_a720, CVE(2022, 23960) 86 87check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 88 89add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561 90 91check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) 92 93cpu_reset_func_start cortex_a720 94 /* Disable speculative loads */ 95 msr SSBS, xzr 96 enable_mpmm 97cpu_reset_func_end cortex_a720 98 99 /* ---------------------------------------------------- 100 * HW will do the cache maintenance while powering down 101 * ---------------------------------------------------- 102 */ 103func cortex_a720_core_pwr_dwn 104 /* --------------------------------------------------- 105 * Enable CPU power down bit in power control register 106 * --------------------------------------------------- 107 */ 108 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 109 110 isb 111 ret 112endfunc cortex_a720_core_pwr_dwn 113 114 /* --------------------------------------------- 115 * This function provides Cortex A720-specific 116 * register information for crash reporting. 117 * It needs to return with x6 pointing to 118 * a list of register names in ascii and 119 * x8 - x15 having values of registers to be 120 * reported. 121 * --------------------------------------------- 122 */ 123.section .rodata.cortex_a720_regs, "aS" 124cortex_a720_regs: /* The ascii list of register names to be reported */ 125 .asciz "cpuectlr_el1", "" 126 127func cortex_a720_cpu_reg_dump 128 adr x6, cortex_a720_regs 129 mrs x8, CORTEX_A720_CPUECTLR_EL1 130 ret 131endfunc cortex_a720_cpu_reg_dump 132 133declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 134 cortex_a720_reset_func, \ 135 cortex_a720_core_pwr_dwn 136