1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <cortex_a15.h> 11#include <cpu_macros.S> 12 13/* 14 * Cortex-A15 support LPAE and Virtualization Extensions. 15 * Don't care if confiugration uses or not LPAE and VE. 16 * Therefore, where we don't check ARCH_IS_ARMV7_WITH_LPAE/VE 17 */ 18 19 .macro assert_cache_enabled 20#if ENABLE_ASSERTIONS 21 ldcopr r0, SCTLR 22 tst r0, #SCTLR_C_BIT 23 ASM_ASSERT(eq) 24#endif 25 .endm 26 27func cortex_a15_disable_smp 28 ldcopr r0, ACTLR 29 bic r0, #CORTEX_A15_ACTLR_SMP_BIT 30 stcopr r0, ACTLR 31 isb 32 dsb sy 33 bx lr 34endfunc cortex_a15_disable_smp 35 36func cortex_a15_enable_smp 37 ldcopr r0, ACTLR 38 orr r0, #CORTEX_A15_ACTLR_SMP_BIT 39 stcopr r0, ACTLR 40 isb 41 bx lr 42endfunc cortex_a15_enable_smp 43 44func cortex_a15_reset_func 45 b cortex_a15_enable_smp 46endfunc cortex_a15_reset_func 47 48func cortex_a15_core_pwr_dwn 49 push {r12, lr} 50 51 assert_cache_enabled 52 53 /* Flush L1 cache */ 54 mov r0, #DC_OP_CISW 55 bl dcsw_op_level1 56 57 /* Exit cluster coherency */ 58 pop {r12, lr} 59 b cortex_a15_disable_smp 60endfunc cortex_a15_core_pwr_dwn 61 62func cortex_a15_cluster_pwr_dwn 63 push {r12, lr} 64 65 assert_cache_enabled 66 67 /* Flush L1 caches */ 68 mov r0, #DC_OP_CISW 69 bl dcsw_op_level1 70 71 bl plat_disable_acp 72 73 /* Exit cluster coherency */ 74 pop {r12, lr} 75 b cortex_a15_disable_smp 76endfunc cortex_a15_cluster_pwr_dwn 77 78declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \ 79 cortex_a15_reset_func, \ 80 cortex_a15_core_pwr_dwn, \ 81 cortex_a15_cluster_pwr_dwn 82