1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef V2M_DEF_H 7 #define V2M_DEF_H 8 9 #include <arm_xlat_tables.h> 10 11 12 /* V2M motherboard system registers & offsets */ 13 #define V2M_SYSREGS_BASE UL(0x1c010000) 14 #define V2M_SYS_ID UL(0x0) 15 #define V2M_SYS_SWITCH UL(0x4) 16 #define V2M_SYS_LED UL(0x8) 17 #define V2M_SYS_NVFLAGS UL(0x38) 18 #define V2M_SYS_NVFLAGSSET UL(0x38) 19 #define V2M_SYS_NVFLAGSCLR UL(0x3c) 20 #define V2M_SYS_CFGDATA UL(0xa0) 21 #define V2M_SYS_CFGCTRL UL(0xa4) 22 #define V2M_SYS_CFGSTATUS UL(0xa8) 23 24 #define V2M_CFGCTRL_START BIT_32(31) 25 #define V2M_CFGCTRL_RW BIT_32(30) 26 #define V2M_CFGCTRL_FUNC_SHIFT 20 27 #define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT) 28 #define V2M_FUNC_CLK_GEN U(0x01) 29 #define V2M_FUNC_TEMP U(0x04) 30 #define V2M_FUNC_DB_RESET U(0x05) 31 #define V2M_FUNC_SCC_CFG U(0x06) 32 #define V2M_FUNC_SHUTDOWN U(0x08) 33 #define V2M_FUNC_REBOOT U(0x09) 34 35 /* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */ 36 #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) 37 38 /* 39 * V2M sysled bit definitions. The values written to this 40 * register are defined in arch.h & runtime_svc.h. Only 41 * used by the primary cpu to diagnose any cold boot issues. 42 * 43 * SYS_LED[0] - Security state (S=0/NS=1) 44 * SYS_LED[2:1] - Exception Level (EL3-EL0) 45 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 46 * 47 */ 48 #define V2M_SYS_LED_SS_SHIFT 0x0 49 #define V2M_SYS_LED_EL_SHIFT 0x1 50 #define V2M_SYS_LED_EC_SHIFT 0x3 51 52 #define V2M_SYS_LED_SS_MASK 0x1 53 #define V2M_SYS_LED_EL_MASK 0x3 54 #define V2M_SYS_LED_EC_MASK 0x1f 55 56 /* V2M sysid register bits */ 57 #define V2M_SYS_ID_REV_SHIFT 28 58 #define V2M_SYS_ID_HBI_SHIFT 16 59 #define V2M_SYS_ID_BLD_SHIFT 12 60 #define V2M_SYS_ID_ARCH_SHIFT 8 61 #define V2M_SYS_ID_FPGA_SHIFT 0 62 63 #define V2M_SYS_ID_REV_MASK 0xf 64 #define V2M_SYS_ID_HBI_MASK 0xfff 65 #define V2M_SYS_ID_BLD_MASK 0xf 66 #define V2M_SYS_ID_ARCH_MASK 0xf 67 #define V2M_SYS_ID_FPGA_MASK 0xff 68 69 #define V2M_SYS_ID_BLD_LENGTH 4 70 71 72 /* NOR Flash */ 73 #define V2M_FLASH0_BASE 0x08000000 74 #define V2M_FLASH0_SIZE 0x04000000 75 #define V2M_FLASH_BLOCK_SIZE 0x00040000 /* 256 KB */ 76 77 #define V2M_IOFPGA_BASE 0x1c000000 78 #define V2M_IOFPGA_SIZE 0x03000000 79 80 /* PL011 UART related constants */ 81 #define V2M_IOFPGA_UART0_BASE 0x1c090000 82 #define V2M_IOFPGA_UART1_BASE 0x1c0a0000 83 #define V2M_IOFPGA_UART2_BASE 0x1c0b0000 84 #define V2M_IOFPGA_UART3_BASE 0x1c0c0000 85 86 #define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 87 #define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 88 #define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000 89 #define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 90 91 /* SP804 timer related constants */ 92 #define V2M_SP804_TIMER0_BASE 0x1C110000 93 #define V2M_SP804_TIMER1_BASE 0x1C120000 94 95 /* SP810 controller */ 96 #define V2M_SP810_BASE 0x1c020000 97 #define V2M_SP810_CTRL_TIM0_SEL (1 << 15) 98 #define V2M_SP810_CTRL_TIM1_SEL (1 << 17) 99 #define V2M_SP810_CTRL_TIM2_SEL (1 << 19) 100 #define V2M_SP810_CTRL_TIM3_SEL (1 << 21) 101 102 /* 103 * The flash can be mapped either as read-only or read-write. 104 * 105 * If it is read-write then it should also be mapped as device memory because 106 * NOR flash programming involves sending a fixed, ordered sequence of commands. 107 * 108 * If it is read-only then it should also be mapped as: 109 * - Normal memory, because reading from NOR flash is transparent, it is like 110 * reading from RAM. 111 * - Non-executable by default. If some parts of the flash need to be executable 112 * then platform code is responsible for re-mapping the appropriate portion 113 * of it as executable. 114 */ 115 #define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 116 V2M_FLASH0_SIZE, \ 117 MT_DEVICE | MT_RW | MT_SECURE) 118 119 #define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 120 V2M_FLASH0_SIZE, \ 121 MT_RO_DATA | MT_SECURE) 122 123 #define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\ 124 V2M_IOFPGA_SIZE, \ 125 MT_DEVICE | MT_RW | MT_SECURE) 126 127 /* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */ 128 #define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \ 129 V2M_IOFPGA_BASE, \ 130 V2M_IOFPGA_SIZE, \ 131 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 132 133 134 #endif /* V2M_DEF_H */ 135