1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef AMU_H 8 #define AMU_H 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 13 #include <lib/cassert.h> 14 #include <lib/utils_def.h> 15 16 #include <platform_def.h> 17 18 /* All group 0 counters */ 19 #define AMU_GROUP0_COUNTERS_MASK U(0xf) 20 #define AMU_GROUP0_NR_COUNTERS U(4) 21 22 #ifdef PLAT_AMU_GROUP1_COUNTERS_MASK 23 #define AMU_GROUP1_COUNTERS_MASK PLAT_AMU_GROUP1_COUNTERS_MASK 24 #else 25 #define AMU_GROUP1_COUNTERS_MASK U(0) 26 #endif 27 28 /* Calculate number of group 1 counters */ 29 #if (AMU_GROUP1_COUNTERS_MASK & (1 << 15)) 30 #define AMU_GROUP1_NR_COUNTERS 16U 31 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14)) 32 #define AMU_GROUP1_NR_COUNTERS 15U 33 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13)) 34 #define AMU_GROUP1_NR_COUNTERS 14U 35 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12)) 36 #define AMU_GROUP1_NR_COUNTERS 13U 37 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11)) 38 #define AMU_GROUP1_NR_COUNTERS 12U 39 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10)) 40 #define AMU_GROUP1_NR_COUNTERS 11U 41 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9)) 42 #define AMU_GROUP1_NR_COUNTERS 10U 43 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8)) 44 #define AMU_GROUP1_NR_COUNTERS 9U 45 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7)) 46 #define AMU_GROUP1_NR_COUNTERS 8U 47 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6)) 48 #define AMU_GROUP1_NR_COUNTERS 7U 49 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5)) 50 #define AMU_GROUP1_NR_COUNTERS 6U 51 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4)) 52 #define AMU_GROUP1_NR_COUNTERS 5U 53 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3)) 54 #define AMU_GROUP1_NR_COUNTERS 4U 55 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2)) 56 #define AMU_GROUP1_NR_COUNTERS 3U 57 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1)) 58 #define AMU_GROUP1_NR_COUNTERS 2U 59 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0)) 60 #define AMU_GROUP1_NR_COUNTERS 1U 61 #else 62 #define AMU_GROUP1_NR_COUNTERS 0U 63 #endif 64 65 CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask); 66 67 struct amu_ctx { 68 uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS]; 69 #if __aarch64__ 70 /* Architected event counter 1 does not have an offset register. */ 71 uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1]; 72 #endif 73 74 #if AMU_GROUP1_NR_COUNTERS 75 uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS]; 76 #if __aarch64__ 77 uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS]; 78 #endif 79 #endif 80 }; 81 82 unsigned int amu_get_version(void); 83 void amu_enable(bool el2_unused); 84 85 /* Group 0 configuration helpers */ 86 uint64_t amu_group0_cnt_read(unsigned int idx); 87 void amu_group0_cnt_write(unsigned int idx, uint64_t val); 88 89 #if __aarch64__ 90 uint64_t amu_group0_voffset_read(unsigned int idx); 91 void amu_group0_voffset_write(unsigned int idx, uint64_t val); 92 #endif 93 94 #if AMU_GROUP1_NR_COUNTERS 95 bool amu_group1_supported(void); 96 97 /* Group 1 configuration helpers */ 98 uint64_t amu_group1_cnt_read(unsigned int idx); 99 void amu_group1_cnt_write(unsigned int idx, uint64_t val); 100 void amu_group1_set_evtype(unsigned int idx, unsigned int val); 101 102 #if __aarch64__ 103 uint64_t amu_group1_voffset_read(unsigned int idx); 104 void amu_group1_voffset_write(unsigned int idx, uint64_t val); 105 #endif 106 107 #endif 108 109 #endif /* AMU_H */ 110