1 /* 2 * Copyright (c) 2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _WA_CVE_2025_0647_CPPRCTX_H_ 8 #define _WA_CVE_2025_0647_CPPRCTX_H_ 9 10 #ifndef __ASSEMBLER__ 11 12 #include <stdint.h> 13 14 /* 15 * API to perform CPP RCTX instruction functionality in EL3 16 * 17 * Rather than trapping EL3 to EL3 if CPP RCTX is needed, it is simpler to just 18 * have an API that performs the workaround steps. TF-A does not support nested 19 * exceptions outside of specific circumstances, and enabling that generically 20 * is not trivial, so this is a simpler and faster solution. 21 * 22 * The workaround is not reliant on the config register passed to the CPP RCTX 23 * instruction, but the argument is included for compatibility in systems that 24 * might have some cores that need the workaround and some that do not. If the 25 * workaround is not needed, the argument will be used in a normal CPP RCTX call 26 * rather than the workaround procedure. 27 */ 28 void wa_cve_2025_0647_execute_cpp_el3(uint64_t arg); 29 30 #endif 31 32 /* 33 * System register definitions used in this workaround 34 * 35 * Some of these definitions exist in CPU-specific header files but for the 36 * purposes of this workaround it is convenient to have them all here. Currently 37 * all CPUs affected by this issue share these definitions, but if future CPUs 38 * have different register mappings this will need to be updated to pull from 39 * the CPU-specific headers instead. 40 */ 41 42 #define WA_CPUACTLR_EL1 S3_0_C15_C1_0 43 #define WA_CPUACTLR2_EL1 S3_0_C15_C1_1 44 #define WA_CPUECTLR_EL1 S3_0_C15_C1_4 45 #define WA_CPUPSELR_EL3 S3_6_C15_C8_0 46 #define WA_CPUPCR_EL3 S3_6_C15_C8_1 47 #define WA_CPUPOR_EL3 S3_6_C15_C8_2 48 #define WA_CPUPMR_EL3 S3_6_C15_C8_3 49 50 /* Flags passed to workaround function in X0. */ 51 #define WA_IS_TRAP_HANDLER_BIT (0) 52 #define WA_IS_TRAP_HANDLER BIT(WA_IS_TRAP_HANDLER_BIT) 53 #define WA_LS_RCG_EN_BIT (1) 54 #define WA_LS_RCG_EN BIT(WA_LS_RCG_EN_BIT) 55 56 /* Fields passed to init function in X0. */ 57 #define WA_USE_T32_OPCODE_SHIFT (3) 58 #define WA_USE_T32_OPCODE BIT(WA_USE_T32_OPCODE_SHIFT) 59 #define WA_PATCH_SLOT_MASK (0x7) 60 #define WA_PATCH_SLOT(x) (x & WA_PATCH_SLOT_MASK) 61 62 #endif /* _WA_CVE_2025_0647_CPPRCTX_H_ */ 63