| #
fce63f18 |
| 29-Oct-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "gr/spectre_bhb_updates" into integration
* changes:
fix(security): remove CVE_2022_23960 Cortex-X4
fix(security): remove CVE_2022_23960 Neoverse V3
fix(security): rem
Merge changes from topic "gr/spectre_bhb_updates" into integration
* changes:
fix(security): remove CVE_2022_23960 Cortex-X4
fix(security): remove CVE_2022_23960 Neoverse V3
fix(security): remove CVE_2022_23960 Cortex-A720
show more ...
|
| #
a2e22acf |
| 27-Oct-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
fix(security): remove CVE_2022_23960 Neoverse V3
Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.
Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https
fix(security): remove CVE_2022_23960 Neoverse V3
Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.
Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/107734/0002/The-Neoverse--V3--core/Supported-standards-and-specifications?lang=en
Remove WORKAROUND_CVE_2022_23960 to avoid accidental enabling of this
workaround and using loop workaround.
This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670
Change-Id: I13b27c04c3da5ec80fa79422b4ef4fee64738caa
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
show more ...
|
| #
bfecea00 |
| 03-Feb-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "gr/errata_ICH_VMCR_EL2" into integration
* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3701767
fix(cpus): workaround for Neoverse-N3 erratum 3699563
fix(cp
Merge changes from topic "gr/errata_ICH_VMCR_EL2" into integration
* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3701767
fix(cpus): workaround for Neoverse-N3 erratum 3699563
fix(cpus): workaround for Neoverse-N2 erratum 3701773
fix(cpus): workaround for Cortex-X925 erratum 3701747
fix(cpus): workaround for Cortex-X4 erratum 3701758
fix(cpus): workaround for Cortex-X3 erratum 3701769
fix(cpus): workaround for Cortex-X2 erratum 3701772
fix(cpus): workaround for Cortex-A725 erratum 3699564
fix(cpus): workaround for Cortex-A720-AE erratum 3699562
fix(cpus): workaround for Cortex-A720 erratum 3699561
fix(cpus): workaround for Cortex-A715 erratum 3699560
fix(cpus): workaround for Cortex-A710 erratum 3701772
fix(cpus): workaround for accessing ICH_VMCR_EL2
chore(cpus): fix incorrect header macro
show more ...
|
| #
e25fc9df |
| 22-Jan-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
fix(cpus): workaround for Neoverse-V3 erratum 3701767
Neoverse-V3 erratum 3701767 that applies to r0p0, r0p1, r0p2 is
still Open.
The workaround is for EL3 software that performs context save/resto
fix(cpus): workaround for Neoverse-V3 erratum 3701767
Neoverse-V3 erratum 3701767 that applies to r0p0, r0p1, r0p2 is
still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958/latest/
Change-Id: I5be0de881f408a9e82a07b8459d79490e9065f94
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
show more ...
|
| #
1f2c58b1 |
| 31-Jan-2025 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "ar/smccc_arch_wa_4" into integration
* changes:
fix(security): apply SMCCC_ARCH_WORKAROUND_4 to affected cpus
fix(security): add support in cpu_ops for CVE-2024-7881
Merge changes from topic "ar/smccc_arch_wa_4" into integration
* changes:
fix(security): apply SMCCC_ARCH_WORKAROUND_4 to affected cpus
fix(security): add support in cpu_ops for CVE-2024-7881
fix(security): add CVE-2024-7881 mitigation to Cortex-X3
fix(security): add CVE-2024-7881 mitigation to Neoverse-V3
fix(security): add CVE-2024-7881 mitigation to Neoverse-V2
fix(security): add CVE-2024-7881 mitigation to Cortex-X925
fix(security): add CVE-2024-7881 mitigation to Cortex-X4
fix(security): enable WORKAROUND_CVE_2024_7881 build option
show more ...
|
| #
037a15f5 |
| 06-Sep-2024 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(security): add CVE-2024-7881 mitigation to Neoverse-V3
This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1
for Neoverse-V3 CPU.
[1]: https://developer.arm.com/Arm%20Securit
fix(security): add CVE-2024-7881 mitigation to Neoverse-V3
This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1
for Neoverse-V3 CPU.
[1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ib5c644895b8c76d3c7e8b5e6e98d7b9afef7f1ec
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|
| #
ff8e68c0 |
| 26-Mar-2024 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "chore: rename Poseidon to Neoverse V3" into integration
|
| #
328d304d |
| 07-Mar-2024 |
Sona Mathew <sonarebecca.mathew@arm.com> |
chore: rename Poseidon to Neoverse V3
Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.
Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Sign
chore: rename Poseidon to Neoverse V3
Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.
Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
show more ...
|