1*328d304dSSona Mathew /* 2*328d304dSSona Mathew * Copyright (c) 2022-2024, Arm Limited. All rights reserved. 3*328d304dSSona Mathew * 4*328d304dSSona Mathew * SPDX-License-Identifier: BSD-3-Clause 5*328d304dSSona Mathew */ 6*328d304dSSona Mathew 7*328d304dSSona Mathew #ifndef NEOVERSE_V3_H 8*328d304dSSona Mathew #define NEOVERSE_V3_H 9*328d304dSSona Mathew 10*328d304dSSona Mathew 11*328d304dSSona Mathew #define NEOVERSE_V3_VNAE_MIDR U(0x410FD830) 12*328d304dSSona Mathew #define NEOVERSE_V3_MIDR U(0x410FD840) 13*328d304dSSona Mathew 14*328d304dSSona Mathew /* Neoverse V3 loop count for CVE-2022-23960 mitigation */ 15*328d304dSSona Mathew #define NEOVERSE_V3_BHB_LOOP_COUNT U(132) 16*328d304dSSona Mathew 17*328d304dSSona Mathew /******************************************************************************* 18*328d304dSSona Mathew * CPU Extended Control register specific definitions. 19*328d304dSSona Mathew ******************************************************************************/ 20*328d304dSSona Mathew #define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4 21*328d304dSSona Mathew 22*328d304dSSona Mathew /******************************************************************************* 23*328d304dSSona Mathew * CPU Power Control register specific definitions 24*328d304dSSona Mathew ******************************************************************************/ 25*328d304dSSona Mathew #define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 26*328d304dSSona Mathew #define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 27*328d304dSSona Mathew 28*328d304dSSona Mathew #endif /* NEOVERSE_V3_H */ 29