1328d304dSSona Mathew /* 2*037a15f5SArvind Ram Prakash * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3328d304dSSona Mathew * 4328d304dSSona Mathew * SPDX-License-Identifier: BSD-3-Clause 5328d304dSSona Mathew */ 6328d304dSSona Mathew 7328d304dSSona Mathew #ifndef NEOVERSE_V3_H 8328d304dSSona Mathew #define NEOVERSE_V3_H 9328d304dSSona Mathew 10328d304dSSona Mathew 11328d304dSSona Mathew #define NEOVERSE_V3_VNAE_MIDR U(0x410FD830) 12328d304dSSona Mathew #define NEOVERSE_V3_MIDR U(0x410FD840) 13328d304dSSona Mathew 14328d304dSSona Mathew /* Neoverse V3 loop count for CVE-2022-23960 mitigation */ 15328d304dSSona Mathew #define NEOVERSE_V3_BHB_LOOP_COUNT U(132) 16328d304dSSona Mathew 17328d304dSSona Mathew /******************************************************************************* 18328d304dSSona Mathew * CPU Extended Control register specific definitions. 19328d304dSSona Mathew ******************************************************************************/ 20328d304dSSona Mathew #define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4 21328d304dSSona Mathew 22328d304dSSona Mathew /******************************************************************************* 23328d304dSSona Mathew * CPU Power Control register specific definitions 24328d304dSSona Mathew ******************************************************************************/ 25328d304dSSona Mathew #define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 26328d304dSSona Mathew #define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 27328d304dSSona Mathew 28*037a15f5SArvind Ram Prakash /******************************************************************************* 29*037a15f5SArvind Ram Prakash * CPU Auxiliary control register 6 specific definitions 30*037a15f5SArvind Ram Prakash ******************************************************************************/ 31*037a15f5SArvind Ram Prakash #define NEOVERSE_V3_CPUACTLR6_EL1 S3_0_C15_C8_1 32*037a15f5SArvind Ram Prakash 33328d304dSSona Mathew #endif /* NEOVERSE_V3_H */ 34