1ba6b6949SGovindraj Raja /* 2*fded8392SGovindraj Raja * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3ba6b6949SGovindraj Raja * 4ba6b6949SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5ba6b6949SGovindraj Raja */ 6ba6b6949SGovindraj Raja 7ba6b6949SGovindraj Raja #ifndef NEOVERSE_N3_H 8ba6b6949SGovindraj Raja #define NEOVERSE_N3_H 9ba6b6949SGovindraj Raja 10ba6b6949SGovindraj Raja #define NEOVERSE_N3_MIDR U(0x410FD8E0) 11ba6b6949SGovindraj Raja 12ba6b6949SGovindraj Raja /******************************************************************************* 13ba6b6949SGovindraj Raja * CPU Extended Control register specific definitions 14ba6b6949SGovindraj Raja ******************************************************************************/ 15ba6b6949SGovindraj Raja #define NEOVERSE_N3_CPUECTLR_EL1 S3_0_C15_C1_4 166fbc98b1SYounghyun Park #define NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 17ba6b6949SGovindraj Raja 18ba6b6949SGovindraj Raja /******************************************************************************* 19ba6b6949SGovindraj Raja * CPU Power Control register specific definitions 20ba6b6949SGovindraj Raja ******************************************************************************/ 21ba6b6949SGovindraj Raja #define NEOVERSE_N3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22ba6b6949SGovindraj Raja #define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 23ba6b6949SGovindraj Raja 24*fded8392SGovindraj Raja #ifndef __ASSEMBLER__ 25*fded8392SGovindraj Raja long check_erratum_neoverse_n3_3699563(long cpu_rev); 26*fded8392SGovindraj Raja #endif /* __ASSEMBLER__ */ 27*fded8392SGovindraj Raja 28ba6b6949SGovindraj Raja #endif /* NEOVERSE_N3_H */ 29