| #
6dacf15c |
| 18-Sep-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(cpus): fix external LLC presence bit in Neoverse N3" into integration
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| #
ff90ce41 |
| 26-Aug-2025 |
Younghyun Park <younghyunpark@google.com> |
feat(cpus): fix external LLC presence bit in Neoverse N3
Unlike Neoverse N2, Neoverse N3 incorporates the External LLC presence
bit in CPUECTLR2_EL1.SW_EXT_LLC. In addition, the default value is
ext
feat(cpus): fix external LLC presence bit in Neoverse N3
Unlike Neoverse N2, Neoverse N3 incorporates the External LLC presence
bit in CPUECTLR2_EL1.SW_EXT_LLC. In addition, the default value is
external LLC in Neoverse N3, so the bit will be cleared when
NEOVERSE_Nx_EXTERNAL_LLC is not enabled.
Change-Id: I1182aba5423e74748efd2571cc3817634ada748d
Signed-off-by: Younghyun Park <younghyunpark@google.com>
show more ...
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| #
bfecea00 |
| 03-Feb-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "gr/errata_ICH_VMCR_EL2" into integration
* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3701767
fix(cpus): workaround for Neoverse-N3 erratum 3699563
fix(cp
Merge changes from topic "gr/errata_ICH_VMCR_EL2" into integration
* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3701767
fix(cpus): workaround for Neoverse-N3 erratum 3699563
fix(cpus): workaround for Neoverse-N2 erratum 3701773
fix(cpus): workaround for Cortex-X925 erratum 3701747
fix(cpus): workaround for Cortex-X4 erratum 3701758
fix(cpus): workaround for Cortex-X3 erratum 3701769
fix(cpus): workaround for Cortex-X2 erratum 3701772
fix(cpus): workaround for Cortex-A725 erratum 3699564
fix(cpus): workaround for Cortex-A720-AE erratum 3699562
fix(cpus): workaround for Cortex-A720 erratum 3699561
fix(cpus): workaround for Cortex-A715 erratum 3699560
fix(cpus): workaround for Cortex-A710 erratum 3701772
fix(cpus): workaround for accessing ICH_VMCR_EL2
chore(cpus): fix incorrect header macro
show more ...
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| #
fded8392 |
| 22-Jan-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
fix(cpus): workaround for Neoverse-N3 erratum 3699563
Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open.
The workaround is for EL3 software that performs context save/restore
on a chan
fix(cpus): workaround for Neoverse-N3 erratum 3699563
Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3050973/latest/
Change-Id: I77aaf8ae0afff3adde9a85f4a1a13ac9d1daf0af
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
show more ...
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| #
332b62e0 |
| 10-May-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(cpus): support to update External LLC presence in Neoverse N3" into integration
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| #
6fbc98b1 |
| 09-May-2024 |
Younghyun Park <younghyunpark@google.com> |
feat(cpus): support to update External LLC presence in Neoverse N3
The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is interna
feat(cpus): support to update External LLC presence in Neoverse N3
The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with the build option 'NEOVERSE_Nx_EXTERNAL_LLC'.
Change-Id: I2567283a55c0d6e2f9fd986b7dbab91c7a815d3d
Signed-off-by: Younghyun Park <younghyunpark@google.com>
show more ...
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| #
2b67ee6d |
| 08-May-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "chore: rename hermes to neoverse-n3" into integration
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| #
ba6b6949 |
| 06-May-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hermes to neoverse-n3
Rename hermes cpu to Neoverse-N3
Change-Id: I912d4c824c5004a8c1909c68fef77f1f5e202b8a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|