1*ba6b6949SGovindraj Raja /* 2*ba6b6949SGovindraj Raja * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3*ba6b6949SGovindraj Raja * 4*ba6b6949SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5*ba6b6949SGovindraj Raja */ 6*ba6b6949SGovindraj Raja 7*ba6b6949SGovindraj Raja #ifndef NEOVERSE_N3_H 8*ba6b6949SGovindraj Raja #define NEOVERSE_N3_H 9*ba6b6949SGovindraj Raja 10*ba6b6949SGovindraj Raja #define NEOVERSE_N3_MIDR U(0x410FD8E0) 11*ba6b6949SGovindraj Raja 12*ba6b6949SGovindraj Raja /******************************************************************************* 13*ba6b6949SGovindraj Raja * CPU Extended Control register specific definitions 14*ba6b6949SGovindraj Raja ******************************************************************************/ 15*ba6b6949SGovindraj Raja #define NEOVERSE_N3_CPUECTLR_EL1 S3_0_C15_C1_4 16*ba6b6949SGovindraj Raja 17*ba6b6949SGovindraj Raja /******************************************************************************* 18*ba6b6949SGovindraj Raja * CPU Power Control register specific definitions 19*ba6b6949SGovindraj Raja ******************************************************************************/ 20*ba6b6949SGovindraj Raja #define NEOVERSE_N3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21*ba6b6949SGovindraj Raja #define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 22*ba6b6949SGovindraj Raja 23*ba6b6949SGovindraj Raja #endif /* NEOVERSE_N3_H */ 24