1 /* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X2_H 8 #define CORTEX_X2_H 9 10 #define CORTEX_X2_MIDR U(0x410FD480) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 16 #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 17 18 /******************************************************************************* 19 * CPU Extended Control register 2 specific definitions 20 ******************************************************************************/ 21 #define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5 22 23 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11) 24 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 25 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) 26 27 /******************************************************************************* 28 * CPU Power Control register specific definitions 29 ******************************************************************************/ 30 #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 31 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 32 33 /******************************************************************************* 34 * CPU Auxiliary Control Register 5 definitions 35 ******************************************************************************/ 36 #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 37 #define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 38 39 /******************************************************************************* 40 * CPU Implementation Specific Selected Instruction registers 41 ******************************************************************************/ 42 #define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 43 #define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 44 #define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 45 #define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 46 47 #endif /* CORTEX_X2_H */ 48