1 /* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A78C_H 8 #define CORTEX_A78C_H 9 10 11 #define CORTEX_A78C_MIDR U(0x410FD4B1) 12 13 /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 14 #define CORTEX_A78C_BHB_LOOP_COUNT U(32) 15 16 /******************************************************************************* 17 * CPU Extended Control register specific definitions. 18 ******************************************************************************/ 19 #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 20 #define CORTEX_A78C_CPUECTLR_EL1_BIT6 (ULL(1) << 6) 21 #define CORTEX_A78C_CPUECTLR_EL1_BIT7 (ULL(1) << 7) 22 23 /******************************************************************************* 24 * CPU Power Control register specific definitions 25 ******************************************************************************/ 26 #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 27 #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 28 29 #endif /* CORTEX_A78C_H */ 30