1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CORTEX_A53_H__ 32 #define __CORTEX_A53_H__ 33 34 /* Cortex-A53 midr for revision 0 */ 35 #define CORTEX_A53_MIDR 0x410FD030 36 37 /* Retention timer tick definitions */ 38 #define RETENTION_ENTRY_TICKS_2 0x1 39 #define RETENTION_ENTRY_TICKS_8 0x2 40 #define RETENTION_ENTRY_TICKS_32 0x3 41 #define RETENTION_ENTRY_TICKS_64 0x4 42 #define RETENTION_ENTRY_TICKS_128 0x5 43 #define RETENTION_ENTRY_TICKS_256 0x6 44 #define RETENTION_ENTRY_TICKS_512 0x7 45 46 /******************************************************************************* 47 * CPU Extended Control register specific definitions. 48 ******************************************************************************/ 49 #define CPUECTLR p15, 1, c15 /* Instruction def. */ 50 51 #define CPUECTLR_SMP_BIT (1 << 6) 52 53 #define CPUECTLR_CPU_RET_CTRL_SHIFT 0 54 #define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) 55 56 #define CPUECTLR_FPU_RET_CTRL_SHIFT 3 57 #define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) 58 59 /******************************************************************************* 60 * CPU Memory Error Syndrome register specific definitions. 61 ******************************************************************************/ 62 #define CPUMERRSR p15, 2, c15 /* Instruction def. */ 63 64 /******************************************************************************* 65 * CPU Auxiliary Control register specific definitions. 66 ******************************************************************************/ 67 #define CPUACTLR p15, 0, c15 /* Instruction def. */ 68 69 #define CPUACTLR_DTAH (1 << 24) 70 71 /******************************************************************************* 72 * L2 Auxiliary Control register specific definitions. 73 ******************************************************************************/ 74 #define L2ACTLR p15, 1, c15, c0, 0 /* Instruction def. */ 75 76 #define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) 77 #define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) 78 79 /******************************************************************************* 80 * L2 Extended Control register specific definitions. 81 ******************************************************************************/ 82 #define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */ 83 84 #define L2ECTLR_RET_CTRL_SHIFT 0 85 #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) 86 87 /******************************************************************************* 88 * L2 Memory Error Syndrome register specific definitions. 89 ******************************************************************************/ 90 #define L2MERRSR p15, 3, c15 /* Instruction def. */ 91 92 #endif /* __CORTEX_A53_H__ */ 93