1 /* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A53_H 8 #define CORTEX_A53_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A53 midr for revision 0 */ 13 #define CORTEX_A53_MIDR 0x410FD030 14 15 /* Retention timer tick definitions */ 16 #define RETENTION_ENTRY_TICKS_2 0x1 17 #define RETENTION_ENTRY_TICKS_8 0x2 18 #define RETENTION_ENTRY_TICKS_32 0x3 19 #define RETENTION_ENTRY_TICKS_64 0x4 20 #define RETENTION_ENTRY_TICKS_128 0x5 21 #define RETENTION_ENTRY_TICKS_256 0x6 22 #define RETENTION_ENTRY_TICKS_512 0x7 23 24 /******************************************************************************* 25 * CPU Extended Control register specific definitions. 26 ******************************************************************************/ 27 #define CORTEX_A53_ECTLR p15, 1, c15 28 29 #define CORTEX_A53_ECTLR_SMP_BIT (1 << 6) 30 31 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0 32 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) 33 34 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3 35 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) 36 37 /******************************************************************************* 38 * CPU Memory Error Syndrome register specific definitions. 39 ******************************************************************************/ 40 #define CORTEX_A53_MERRSR p15, 2, c15 41 42 /******************************************************************************* 43 * CPU Auxiliary Control register specific definitions. 44 ******************************************************************************/ 45 #define CORTEX_A53_CPUACTLR p15, 0, c15 46 47 #define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT U(44) 48 #define CORTEX_A53_CPUACTLR_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT) 49 #define CORTEX_A53_CPUACTLR_DTAH_SHIFT U(24) 50 #define CORTEX_A53_CPUACTLR_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_DTAH_SHIFT) 51 52 /******************************************************************************* 53 * L2 Auxiliary Control register specific definitions. 54 ******************************************************************************/ 55 #define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0 56 57 #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) 58 #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) 59 60 /******************************************************************************* 61 * L2 Extended Control register specific definitions. 62 ******************************************************************************/ 63 #define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3 64 65 #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0 66 #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) 67 68 /******************************************************************************* 69 * L2 Memory Error Syndrome register specific definitions. 70 ******************************************************************************/ 71 #define CORTEX_A53_L2MERRSR p15, 3, c15 72 73 #endif /* CORTEX_A53_H */ 74