1dc787588SYatharth Kochar /* 2*4c700c15SGovindraj Raja * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. 3dc787588SYatharth Kochar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5dc787588SYatharth Kochar */ 6dc787588SYatharth Kochar 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A53_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A53_H 9dc787588SYatharth Kochar 10a69817edSAntonio Nino Diaz #include <lib/utils_def.h> 11a69817edSAntonio Nino Diaz 12dc787588SYatharth Kochar /* Cortex-A53 midr for revision 0 */ 131a74e4a8SAntonio Nino Diaz #define CORTEX_A53_MIDR U(0x410FD030) 14dc787588SYatharth Kochar 15dc787588SYatharth Kochar /* Retention timer tick definitions */ 161a74e4a8SAntonio Nino Diaz #define RETENTION_ENTRY_TICKS_2 U(0x1) 171a74e4a8SAntonio Nino Diaz #define RETENTION_ENTRY_TICKS_8 U(0x2) 181a74e4a8SAntonio Nino Diaz #define RETENTION_ENTRY_TICKS_32 U(0x3) 191a74e4a8SAntonio Nino Diaz #define RETENTION_ENTRY_TICKS_64 U(0x4) 201a74e4a8SAntonio Nino Diaz #define RETENTION_ENTRY_TICKS_128 U(0x5) 211a74e4a8SAntonio Nino Diaz #define RETENTION_ENTRY_TICKS_256 U(0x6) 221a74e4a8SAntonio Nino Diaz #define RETENTION_ENTRY_TICKS_512 U(0x7) 23dc787588SYatharth Kochar 24dc787588SYatharth Kochar /******************************************************************************* 25dc787588SYatharth Kochar * CPU Extended Control register specific definitions. 26dc787588SYatharth Kochar ******************************************************************************/ 27fb7d32e5SVarun Wadekar #define CORTEX_A53_ECTLR p15, 1, c15 28dc787588SYatharth Kochar 291a74e4a8SAntonio Nino Diaz #define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) 30dc787588SYatharth Kochar 311a74e4a8SAntonio Nino Diaz #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) 321a74e4a8SAntonio Nino Diaz #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) 33dc787588SYatharth Kochar 341a74e4a8SAntonio Nino Diaz #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) 351a74e4a8SAntonio Nino Diaz #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) 36dc787588SYatharth Kochar 37dc787588SYatharth Kochar /******************************************************************************* 38dc787588SYatharth Kochar * CPU Memory Error Syndrome register specific definitions. 39dc787588SYatharth Kochar ******************************************************************************/ 40fb7d32e5SVarun Wadekar #define CORTEX_A53_MERRSR p15, 2, c15 41dc787588SYatharth Kochar 42dc787588SYatharth Kochar /******************************************************************************* 43dc787588SYatharth Kochar * CPU Auxiliary Control register specific definitions. 44dc787588SYatharth Kochar ******************************************************************************/ 4580bcf981SEleanor Bonnici #define CORTEX_A53_CPUACTLR p15, 0, c15 46dc787588SYatharth Kochar 47a69817edSAntonio Nino Diaz #define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT U(44) 48a69817edSAntonio Nino Diaz #define CORTEX_A53_CPUACTLR_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT) 49a69817edSAntonio Nino Diaz #define CORTEX_A53_CPUACTLR_DTAH_SHIFT U(24) 50a69817edSAntonio Nino Diaz #define CORTEX_A53_CPUACTLR_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_DTAH_SHIFT) 51dc787588SYatharth Kochar 52dc787588SYatharth Kochar /******************************************************************************* 53dc787588SYatharth Kochar * L2 Auxiliary Control register specific definitions. 54dc787588SYatharth Kochar ******************************************************************************/ 55fb7d32e5SVarun Wadekar #define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0 56dc787588SYatharth Kochar 571a74e4a8SAntonio Nino Diaz #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) 581a74e4a8SAntonio Nino Diaz #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) 59dc787588SYatharth Kochar 60dc787588SYatharth Kochar /******************************************************************************* 61dc787588SYatharth Kochar * L2 Extended Control register specific definitions. 62dc787588SYatharth Kochar ******************************************************************************/ 63fb7d32e5SVarun Wadekar #define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3 64dc787588SYatharth Kochar 651a74e4a8SAntonio Nino Diaz #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) 661a74e4a8SAntonio Nino Diaz #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) 67dc787588SYatharth Kochar 68dc787588SYatharth Kochar /******************************************************************************* 69dc787588SYatharth Kochar * L2 Memory Error Syndrome register specific definitions. 70dc787588SYatharth Kochar ******************************************************************************/ 71fb7d32e5SVarun Wadekar #define CORTEX_A53_L2MERRSR p15, 3, c15 72dc787588SYatharth Kochar 73c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A53_H */ 74