1*30c8a20dSKhristine Andreea Barbulescu /* 2*30c8a20dSKhristine Andreea Barbulescu * Copyright 2020-2025 NXP 3*30c8a20dSKhristine Andreea Barbulescu * 4*30c8a20dSKhristine Andreea Barbulescu * SPDX-License-Identifier: BSD-3-Clause 5*30c8a20dSKhristine Andreea Barbulescu */ 6*30c8a20dSKhristine Andreea Barbulescu 7*30c8a20dSKhristine Andreea Barbulescu #ifndef DDR_UTILS_H 8*30c8a20dSKhristine Andreea Barbulescu #define DDR_UTILS_H 9*30c8a20dSKhristine Andreea Barbulescu 10*30c8a20dSKhristine Andreea Barbulescu #include <stdbool.h> 11*30c8a20dSKhristine Andreea Barbulescu #include <stdlib.h> 12*30c8a20dSKhristine Andreea Barbulescu 13*30c8a20dSKhristine Andreea Barbulescu #include <lib/mmio.h> 14*30c8a20dSKhristine Andreea Barbulescu 15*30c8a20dSKhristine Andreea Barbulescu #include <platform_def.h> 16*30c8a20dSKhristine Andreea Barbulescu 17*30c8a20dSKhristine Andreea Barbulescu /* Possible errors */ 18*30c8a20dSKhristine Andreea Barbulescu #define NO_ERR 0x00000000U 19*30c8a20dSKhristine Andreea Barbulescu #define TIMEOUT_ERR 0x00000002U 20*30c8a20dSKhristine Andreea Barbulescu #define TRAINING_FAILED 0x00000003U 21*30c8a20dSKhristine Andreea Barbulescu #define BITFIELD_EXCEEDED 0x00000004U 22*30c8a20dSKhristine Andreea Barbulescu #define DEASSERT_FAILED 0x00000005U 23*30c8a20dSKhristine Andreea Barbulescu 24*30c8a20dSKhristine Andreea Barbulescu #define TRAINING_OK_MSG 0x07U 25*30c8a20dSKhristine Andreea Barbulescu #define TRAINING_FAILED_MSG 0xFFU 26*30c8a20dSKhristine Andreea Barbulescu 27*30c8a20dSKhristine Andreea Barbulescu #define APBONLY_DCTWRITEPROT_ACK_EN 0U 28*30c8a20dSKhristine Andreea Barbulescu #define APBONLY_DCTWRITEPROT_ACK_DIS 1U 29*30c8a20dSKhristine Andreea Barbulescu 30*30c8a20dSKhristine Andreea Barbulescu /* PHY related */ 31*30c8a20dSKhristine Andreea Barbulescu #define DDR_PHYA_APBONLY_UCTSHADOWREGS 0x40380404U 32*30c8a20dSKhristine Andreea Barbulescu #define UCT_WRITE_PROT_SHADOW_MASK 0x1U 33*30c8a20dSKhristine Andreea Barbulescu #define DDR_PHYA_DCTWRITEPROT 0x4038040CU 34*30c8a20dSKhristine Andreea Barbulescu #define DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW 0x40380410U 35*30c8a20dSKhristine Andreea Barbulescu #define UCT_WRITE_PROT_SHADOW_ACK 0x0U 36*30c8a20dSKhristine Andreea Barbulescu 37*30c8a20dSKhristine Andreea Barbulescu /* Default timeout for DDR PHY operations */ 38*30c8a20dSKhristine Andreea Barbulescu #define DEFAULT_TIMEOUT_US 1000000U 39*30c8a20dSKhristine Andreea Barbulescu 40*30c8a20dSKhristine Andreea Barbulescu /* Wait until firmware finishes execution and return training result */ 41*30c8a20dSKhristine Andreea Barbulescu uint32_t wait_firmware_execution(void); 42*30c8a20dSKhristine Andreea Barbulescu 43*30c8a20dSKhristine Andreea Barbulescu #endif /* DDR_UTILS_H */ 44