1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define MHU_TX_ADDR 46240000 /* hex */ 14#define MHU_RX_ADDR 46250000 /* hex */ 15 16#define LIT_CPU_PMU_COMPATIBLE "arm,nevis-pmu" 17#define MID_CPU_PMU_COMPATIBLE "arm,gelas-pmu" 18#define BIG_CPU_PMU_COMPATIBLE "arm,travis-pmu" 19 20#define RSE_MHU_TX_ADDR 49020000 /* hex */ 21#define RSE_MHU_RX_ADDR 49030000 /* hex */ 22 23#if TARGET_FLAVOUR_FVP 24#define ETHERNET_ADDR 64000000 25#define ETHERNET_INT 799 26#define SYS_REGS_ADDR 60080000 27#define MMC_ADDR 600b0000 28#define MMC_INT_0 778 29#define MMC_INT_1 779 30#else /* TARGET_FLAVOUR_FPGA */ 31#define ETHERNET_ADDR 18000000 32#define ETHERNET_INT 109 33#define SYS_REGS_ADDR 1c010000 34#define MMC_ADDR 1c050000 35#define MMC_INT_0 107 36#define MMC_INT_1 108 37#endif /* TARGET_FLAVOUR_FVP */ 38 39#define RTC_ADDR 600a0000 40#define RTC_INT 777 41 42#define KMI_0_ADDR 60100000 43#define KMI_0_INT 784 44#define KMI_1_ADDR 60110000 45#define KMI_1_INT 785 46 47#define VIRTIO_BLOCK_ADDR 60020000 48#define VIRTIO_BLOCK_INT 769 49 50#if TARGET_FLAVOUR_FPGA 51#define DPU_ADDR 4000000000 52#define DPU_IRQ 579 53#endif 54 55#include "tc-common.dtsi" 56#if TARGET_FLAVOUR_FVP 57#include "tc-fvp.dtsi" 58#else 59#include "tc-fpga.dtsi" 60#endif /* TARGET_FLAVOUR_FVP */ 61#include "tc3-4-base.dtsi" 62 63/ { 64 smmu_700: iommu@3f000000 { 65 status = "okay"; 66 }; 67 68 smmu_700_dpu: iommu@4002a00000 { 69 status = "okay"; 70 }; 71 72 dp0: display@DPU_ADDR { 73 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 74 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 75 }; 76 77 gpu: gpu@2d000000 { 78 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>; 79 interrupt-names = "IRQAW"; 80 iommus = <&smmu_700 0x0>; 81 system-coherency = <0x0>; 82 }; 83 84 dsu-pmu { 85 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 86 }; 87 88 cs-pmu@4 { 89 compatible = "arm,coresight-pmu"; 90 reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>; 91 }; 92 93 cs-pmu@5 { 94 compatible = "arm,coresight-pmu"; 95 reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>; 96 }; 97 98 cs-pmu@6 { 99 compatible = "arm,coresight-pmu"; 100 reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>; 101 }; 102 103 cs-pmu@7 { 104 compatible = "arm,coresight-pmu"; 105 reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>; 106 }; 107 108#if defined(TARGET_FLAVOUR_FPGA) 109 slc-msc@0 { 110 compatible = "arm,mpam-msc"; 111 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(0) 0x0 0x4000>; 112 }; 113 114 slc-msc@1 { 115 compatible = "arm,mpam-msc"; 116 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(1) 0x0 0x4000>; 117 }; 118 119 slc-msc@2 { 120 compatible = "arm,mpam-msc"; 121 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(2) 0x0 0x4000>; 122 }; 123 124 slc-msc@3 { 125 compatible = "arm,mpam-msc"; 126 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(3) 0x0 0x4000>; 127 }; 128 129 slc-msc@4 { 130 compatible = "arm,mpam-msc"; 131 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(4) 0x0 0x4000>; 132 }; 133 134 slc-msc@5 { 135 compatible = "arm,mpam-msc"; 136 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(5) 0x0 0x4000>; 137 }; 138 139 slc-msc@6 { 140 compatible = "arm,mpam-msc"; 141 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(6) 0x0 0x4000>; 142 }; 143 144 slc-msc@7 { 145 compatible = "arm,mpam-msc"; 146 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(7) 0x0 0x4000>; 147 }; 148#endif /* TARGET_FLAVOUR_FPGA */ 149}; 150