xref: /rk3399_ARM-atf/fdts/tc4.dts (revision 99f6790cb9681d0a2960f8d30d82c20db19f6ab7)

/*
 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>

#define MHU_TX_ADDR			46240000 /* hex */
#define MHU_RX_ADDR			46250000 /* hex */

#define LIT_CPU_PMU_COMPATIBLE		"arm,armv8-pmuv3"
#define MID_CPU_PMU_COMPATIBLE		"arm,armv8-pmuv3"
#define BIG_CPU_PMU_COMPATIBLE		"arm,armv8-pmuv3"

#define RSE_MHU_TX_ADDR			49020000 /* hex */
#define RSE_MHU_RX_ADDR			49030000 /* hex */

#if TARGET_FLAVOUR_FVP
#define ETHERNET_ADDR			64000000
#define ETHERNET_INT			799
#define SYS_REGS_ADDR			60080000
#define MMC_ADDR			600b0000
#define MMC_INT_0			778
#define MMC_INT_1			779
#else /* TARGET_FLAVOUR_FPGA */
#define ETHERNET_ADDR			18000000
#define ETHERNET_INT			109
#define SYS_REGS_ADDR			1c010000
#define MMC_ADDR			1c050000
#define MMC_INT_0			107
#define MMC_INT_1			108
#endif /* TARGET_FLAVOUR_FVP */

#define RTC_ADDR			600a0000
#define RTC_INT				777

#define KMI_0_ADDR			60100000
#define KMI_0_INT			784
#define KMI_1_ADDR			60110000
#define KMI_1_INT			785

#define VIRTIO_BLOCK_ADDR		60020000
#define VIRTIO_BLOCK_INT		769

#if TARGET_FLAVOUR_FPGA
#define DPU_ADDR			4000000000
#define DPU_IRQ				579
#endif

#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc3-4-base.dtsi"

/ {
	smmu_700: iommu@3f000000 {
		status = "okay";
	};

	smmu_700_dpu: iommu@4002a00000 {
		status = "okay";
	};

	dp0: display@DPU_ADDR {
		iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
			 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
	};

	gpu: gpu@2d000000 {
		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "IRQAW";
		iommus = <&smmu_700 0x0>;
		system-coherency = <0x0>;
	};

	dsu-pmu {
		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	cs-pmu@4 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>;
	};

	cs-pmu@5 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>;
	};

	cs-pmu@6 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>;
	};

	cs-pmu@7 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>;
	};

#if defined(TARGET_FLAVOUR_FPGA)
	slc-msc@0 {
		compatible = "arm,mpam-msc";
		reg = <0x0 MCN_MPAM_NS_BASE_ADDR(0) 0x0 0x4000>;
	};

	slc-msc@1 {
		compatible = "arm,mpam-msc";
		reg = <0x0 MCN_MPAM_NS_BASE_ADDR(1) 0x0 0x4000>;
	};

	slc-msc@2 {
		compatible = "arm,mpam-msc";
		reg = <0x0 MCN_MPAM_NS_BASE_ADDR(2) 0x0 0x4000>;
	};

	slc-msc@3 {
		compatible = "arm,mpam-msc";
		reg = <0x0 MCN_MPAM_NS_BASE_ADDR(3) 0x0 0x4000>;
	};

	slc-msc@4 {
		compatible = "arm,mpam-msc";
		reg = <0x0 MCN_MPAM_NS_BASE_ADDR(4) 0x0 0x4000>;
	};

	slc-msc@5 {
		compatible = "arm,mpam-msc";
		reg = <0x0 MCN_MPAM_NS_BASE_ADDR(5) 0x0 0x4000>;
	};

	slc-msc@6 {
		compatible = "arm,mpam-msc";
		reg = <0x0 MCN_MPAM_NS_BASE_ADDR(6) 0x0 0x4000>;
	};

	slc-msc@7 {
		compatible = "arm,mpam-msc";
		reg = <0x0 MCN_MPAM_NS_BASE_ADDR(7) 0x0 0x4000>;
	};
#endif	/* TARGET_FLAVOUR_FPGA */
};