1/* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#define GIC_CTRL_ADDR 2c010000 8#define GIC_GICR_OFFSET 0x200000 9#define UART_OFFSET 0x1000 10 11#ifdef TC_RESOLUTION_1920X1080P60 12 13#define VENCODER_TIMING_CLK 148500000 14#define VENCODER_TIMING \ 15 clock-frequency = <VENCODER_TIMING_CLK>; \ 16 hactive = <1920>; \ 17 vactive = <1080>; \ 18 hfront-porch = <88>; \ 19 hback-porch = <148>; \ 20 hsync-len = <44>; \ 21 vfront-porch = <4>; \ 22 vback-porch = <36>; \ 23 vsync-len = <5> 24 25#else /* TC_RESOLUTION_640X480P60 */ 26 27#define VENCODER_TIMING_CLK 25175000 28#define VENCODER_TIMING \ 29 clock-frequency = <VENCODER_TIMING_CLK>; \ 30 hactive = <640>; \ 31 vactive = <480>; \ 32 hfront-porch = <16>; \ 33 hback-porch = <48>; \ 34 hsync-len = <96>; \ 35 vfront-porch = <10>; \ 36 vback-porch = <33>; \ 37 vsync-len = <2> 38 39#endif 40 41/ { 42 chosen { 43 stdout-path = "serial0:115200n8"; 44 }; 45 46 ethernet: ethernet@18000000 { 47 compatible = "smsc,lan91c111"; 48 }; 49 50 mmci: mmci@1c050000 { 51 cd-gpios = <&sysreg 0 0>; 52 }; 53 54 rtc@1c170000 { 55 compatible = "arm,pl031", "arm,primecell"; 56 reg = <0x0 0x1C170000 0x0 0x1000>; 57 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 58 clocks = <&soc_refclk>; 59 clock-names = "apb_pclk"; 60 }; 61 62 kmi@1c060000 { 63 compatible = "arm,pl050", "arm,primecell"; 64 reg = <0x0 0x001c060000 0x0 0x1000>; 65 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 66 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 67 clock-names = "KMIREFCLK", "apb_pclk"; 68 }; 69 70 kmi@1c070000 { 71 compatible = "arm,pl050", "arm,primecell"; 72 reg = <0x0 0x001c070000 0x0 0x1000>; 73 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 74 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 75 clock-names = "KMIREFCLK", "apb_pclk"; 76 }; 77 78 virtio_block@1c130000 { 79 compatible = "virtio,mmio"; 80 reg = <0x0 0x1c130000 0x0 0x200>; 81 /* spec lists this wrong */ 82 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 83 }; 84}; 85