xref: /rk3399_ARM-atf/fdts/tc-fvp.dtsi (revision 4e772e6ba3b04f4d18e4f1e3341f86a49b1cfcc8)

/*
 * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#define STDOUT_PATH		"serial0:115200n8"
#define GIC_CTRL_ADDR		2c010000
#define GIC_GICR_OFFSET		0x200000
#define UART_OFFSET		0x1000
#define VENCODER_TIMING_CLK 25175000
#define VENCODER_TIMING								\
	clock-frequency = <VENCODER_TIMING_CLK>;				\
	hactive = <640>;							\
	vactive = <480>;							\
	hfront-porch = <16>;							\
	hback-porch = <48>;							\
	hsync-len = <96>;							\
	vfront-porch = <10>;							\
	vback-porch = <33>;							\
	vsync-len = <2>
#define ETH_COMPATIBLE		"smsc,lan91c111"
#define MMC_REMOVABLE		cd-gpios = <&sysreg 0 0>

/ {
	rtc@1c170000 {
		compatible = "arm,pl031", "arm,primecell";
		reg = <0x0 0x1C170000 0x0 0x1000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_refclk>;
		clock-names = "apb_pclk";
	};

	kmi@1c060000 {
		compatible = "arm,pl050", "arm,primecell";
		reg = <0x0 0x001c060000 0x0 0x1000>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
		clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi@1c070000 {
		compatible = "arm,pl050", "arm,primecell";
		reg = <0x0 0x001c070000 0x0 0x1000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
		clock-names = "KMIREFCLK", "apb_pclk";
	};

	virtio_block@1c130000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c130000 0x0 0x200>;
		/* spec lists this wrong */
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
	};
};