1*35028bd7SLeo Yan/* 2*35028bd7SLeo Yan * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3*35028bd7SLeo Yan * 4*35028bd7SLeo Yan * SPDX-License-Identifier: BSD-3-Clause 5*35028bd7SLeo Yan */ 6*35028bd7SLeo Yan 7*35028bd7SLeo Yan/ { 8*35028bd7SLeo Yan rtc@1c170000 { 9*35028bd7SLeo Yan compatible = "arm,pl031", "arm,primecell"; 10*35028bd7SLeo Yan reg = <0x0 0x1C170000 0x0 0x1000>; 11*35028bd7SLeo Yan interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 12*35028bd7SLeo Yan clocks = <&soc_refclk>; 13*35028bd7SLeo Yan clock-names = "apb_pclk"; 14*35028bd7SLeo Yan }; 15*35028bd7SLeo Yan 16*35028bd7SLeo Yan kmi@1c060000 { 17*35028bd7SLeo Yan compatible = "arm,pl050", "arm,primecell"; 18*35028bd7SLeo Yan reg = <0x0 0x001c060000 0x0 0x1000>; 19*35028bd7SLeo Yan interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 20*35028bd7SLeo Yan clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 21*35028bd7SLeo Yan clock-names = "KMIREFCLK", "apb_pclk"; 22*35028bd7SLeo Yan }; 23*35028bd7SLeo Yan 24*35028bd7SLeo Yan kmi@1c070000 { 25*35028bd7SLeo Yan compatible = "arm,pl050", "arm,primecell"; 26*35028bd7SLeo Yan reg = <0x0 0x001c070000 0x0 0x1000>; 27*35028bd7SLeo Yan interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 28*35028bd7SLeo Yan clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 29*35028bd7SLeo Yan clock-names = "KMIREFCLK", "apb_pclk"; 30*35028bd7SLeo Yan }; 31*35028bd7SLeo Yan 32*35028bd7SLeo Yan virtio_block@1c130000 { 33*35028bd7SLeo Yan compatible = "virtio,mmio"; 34*35028bd7SLeo Yan reg = <0x0 0x1c130000 0x0 0x200>; 35*35028bd7SLeo Yan /* spec lists this wrong */ 36*35028bd7SLeo Yan interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 37*35028bd7SLeo Yan }; 38*35028bd7SLeo Yan}; 39