1/* 2 * Copyright (c) 2020-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#define LIT_CAPACITY 239 8#define MID_CAPACITY 686 9#define BIG_CAPACITY 1024 10 11#define MHU_TX_COMPAT "arm,mhuv3" 12#define MHU_TX_INT_NAME "" 13 14#define MHU_RX_COMPAT "arm,mhuv3" 15#define MHU_OFFSET 0x10000 16#define MHU_MBOX_CELLS 3 17#define MHU_RX_INT_NUM 300 18#define MHU_RX_INT_NAME "combined" 19 20/* If SCMI power domain control is enabled */ 21#if TC_SCMI_PD_CTRL_EN 22#define GPU_SCMI_PD_IDX 0 23#endif /* TC_SCMI_PD_CTRL_EN */ 24 25 26#define DSU_MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ 27 28#if TARGET_FLAVOUR_FVP 29#define DPU_ADDR 4000000000 30#define DPU_IRQ 579 31#endif 32 33/* Use SCMI controlled clocks */ 34#if TC_DPU_USE_SCMI_CLK 35#define DPU_CLK_ATTR1 \ 36 clocks = <&scmi_clk 0>; \ 37 clock-names = "aclk" 38 39#define DPU_CLK_ATTR2 \ 40 clocks = <&scmi_clk 1>; \ 41 clock-names = "pxclk" 42 43#define DPU_CLK_ATTR3 \ 44 clocks = <&scmi_clk 2>; \ 45 clock-names = "pxclk" \ 46/* Use fixed clocks */ 47#else /* !TC_DPU_USE_SCMI_CLK */ 48#define DPU_CLK_ATTR1 \ 49 clocks = <&dpu_aclk>; \ 50 clock-names = "aclk" 51 52#define DPU_CLK_ATTR2 \ 53 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 54 clock-names = "pxclk", "aclk" 55 56#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 57#endif /* !TC_DPU_USE_SCMI_CLK */ 58 59/ { 60 compatible = "arm,tc"; 61 interrupt-parent = <&gic>; 62 #address-cells = <2>; 63 #size-cells = <2>; 64 65 aliases { 66 serial0 = &os_uart; 67 }; 68 69 cpus { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 cpu-map { 74 cluster0 { 75 core0 { 76 cpu = <&CPU0>; 77 }; 78 core1 { 79 cpu = <&CPU1>; 80 }; 81 core2 { 82 cpu = <&CPU2>; 83 }; 84 core3 { 85 cpu = <&CPU3>; 86 }; 87 core4 { 88 cpu = <&CPU4>; 89 }; 90 core5 { 91 cpu = <&CPU5>; 92 }; 93 core6 { 94 cpu = <&CPU6>; 95 }; 96 core7 { 97 cpu = <&CPU7>; 98 }; 99 }; 100 }; 101 102 /* 103 * The timings below are just to demonstrate working cpuidle. 104 * These values may be inaccurate. 105 */ 106 idle-states { 107 entry-method = "psci"; 108 109 CPU_SLEEP_0: cpu-sleep-0 { 110 compatible = "arm,idle-state"; 111 arm,psci-suspend-param = <0x0010000>; 112 local-timer-stop; 113 entry-latency-us = <300>; 114 exit-latency-us = <1200>; 115 min-residency-us = <2000>; 116 }; 117 CLUSTER_SLEEP_0: cluster-sleep-0 { 118 compatible = "arm,idle-state"; 119 arm,psci-suspend-param = <0x1010000>; 120 local-timer-stop; 121 entry-latency-us = <400>; 122 exit-latency-us = <1200>; 123 min-residency-us = <2500>; 124 }; 125 }; 126 127 CPU0:cpu@0 { 128 device_type = "cpu"; 129 compatible = "arm,armv8"; 130 reg = <0x0>; 131 enable-method = "psci"; 132 clocks = <&scmi_dvfs 0>; 133 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 134 capacity-dmips-mhz = <LIT_CAPACITY>; 135 }; 136 137 CPU1:cpu@100 { 138 device_type = "cpu"; 139 compatible = "arm,armv8"; 140 reg = <0x100>; 141 enable-method = "psci"; 142 clocks = <&scmi_dvfs 0>; 143 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 144 capacity-dmips-mhz = <LIT_CAPACITY>; 145 }; 146 147 CPU2:cpu@200 { 148 device_type = "cpu"; 149 compatible = "arm,armv8"; 150 reg = <0x200>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 153 }; 154 155 CPU3:cpu@300 { 156 device_type = "cpu"; 157 compatible = "arm,armv8"; 158 reg = <0x300>; 159 enable-method = "psci"; 160 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 161 }; 162 163 CPU4:cpu@400 { 164 device_type = "cpu"; 165 compatible = "arm,armv8"; 166 reg = <0x400>; 167 enable-method = "psci"; 168 clocks = <&scmi_dvfs 1>; 169 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 170 capacity-dmips-mhz = <MID_CAPACITY>; 171 }; 172 173 CPU5:cpu@500 { 174 device_type = "cpu"; 175 compatible = "arm,armv8"; 176 reg = <0x500>; 177 enable-method = "psci"; 178 clocks = <&scmi_dvfs 1>; 179 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 180 capacity-dmips-mhz = <MID_CAPACITY>; 181 }; 182 183 CPU6:cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,armv8"; 186 reg = <0x600>; 187 enable-method = "psci"; 188 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 189 }; 190 191 CPU7:cpu@700 { 192 device_type = "cpu"; 193 compatible = "arm,armv8"; 194 reg = <0x700>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 197 }; 198 }; 199 200 reserved-memory { 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges; 204 205 linux,cma { 206 compatible = "shared-dma-pool"; 207 reusable; 208 size = <0x0 0x8000000>; 209 linux,cma-default; 210 }; 211 212 optee { 213 compatible = "restricted-dma-pool"; 214 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 215 }; 216 217 }; 218 219 memory { 220 device_type = "memory"; 221 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 222 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 223 HI(PLAT_ARM_DRAM2_SIZE) LO(PLAT_ARM_DRAM2_SIZE)>; 224 }; 225 226 psci { 227 compatible = "arm,psci-1.0", "arm,psci-0.2"; 228 method = "smc"; 229 }; 230 231 cpu-pmu-little { 232 compatible = LIT_CPU_PMU_COMPATIBLE; 233 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>; 234 status = "okay"; 235 }; 236 237 cpu-pmu-mid { 238 compatible = MID_CPU_PMU_COMPATIBLE; 239 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 240 status = "okay"; 241 }; 242 243 cpu-pmu-big { 244 compatible = BIG_CPU_PMU_COMPATIBLE; 245 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 246 status = "okay"; 247 }; 248 249 sram: sram@6000000 { 250 compatible = "mmio-sram"; 251 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 252 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 256 257 cpu_scp_scmi_a2p: scp-shmem@0 { 258 compatible = "arm,scmi-shmem"; 259 reg = <0x0 0x80>; 260 }; 261 }; 262 263 mbox_db_rx: mhu@MHU_RX_ADDR { 264 compatible = MHU_RX_COMPAT; 265 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>; 266 clocks = <&soc_refclk>; 267 clock-names = "apb_pclk"; 268 #mbox-cells = <MHU_MBOX_CELLS>; 269 interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>; 270 interrupt-names = MHU_RX_INT_NAME; 271 }; 272 273 mbox_db_tx: mhu@MHU_TX_ADDR { 274 compatible = MHU_TX_COMPAT; 275 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>; 276 clocks = <&soc_refclk>; 277 clock-names = "apb_pclk"; 278 #mbox-cells = <MHU_MBOX_CELLS>; 279 interrupt-names = MHU_TX_INT_NAME; 280 }; 281 282 firmware { 283 scmi { 284 compatible = "arm,scmi"; 285 mbox-names = "tx", "rx"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289#if TC_SCMI_PD_CTRL_EN 290 scmi_devpd: protocol@11 { 291 reg = <0x11>; 292 #power-domain-cells = <1>; 293 }; 294#endif /* TC_SCMI_PD_CTRL_EN */ 295 296 scmi_dvfs: protocol@13 { 297 reg = <0x13>; 298 #clock-cells = <1>; 299 }; 300 301 scmi_clk: protocol@14 { 302 reg = <0x14>; 303 #clock-cells = <1>; 304 }; 305 }; 306 }; 307 308 gic: interrupt-controller@GIC_CTRL_ADDR { 309 compatible = "arm,gic-v3"; 310 #address-cells = <2>; 311 #interrupt-cells = <4>; 312 #size-cells = <2>; 313 ranges; 314 interrupt-controller; 315 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 316 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 317 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>; 318 }; 319 320 timer { 321 compatible = "arm,armv8-timer"; 322 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 323 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 324 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 325 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 326 }; 327 328 spe-pmu-mid { 329 compatible = "arm,statistical-profiling-extension-v1"; 330 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 331 status = "disabled"; 332 }; 333 334 spe-pmu-big { 335 compatible = "arm,statistical-profiling-extension-v1"; 336 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 337 status = "disabled"; 338 }; 339 340 soc_refclk: refclk { 341 compatible = "fixed-clock"; 342 #clock-cells = <0>; 343 clock-frequency = <1000000000>; 344 clock-output-names = "apb_pclk"; 345 }; 346 347 soc_refclk60mhz: refclk60mhz { 348 compatible = "fixed-clock"; 349 #clock-cells = <0>; 350 clock-frequency = <60000000>; 351 clock-output-names = "iofpga_clk"; 352 }; 353 354 soc_uartclk: uartclk { 355 compatible = "fixed-clock"; 356 #clock-cells = <0>; 357 clock-frequency = <TC_UARTCLK>; 358 clock-output-names = "uartclk"; 359 }; 360 361 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 362 os_uart: serial@2a400000 { 363 compatible = "arm,pl011", "arm,primecell"; 364 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 365 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>; 366 clocks = <&soc_uartclk>, <&soc_refclk>; 367 clock-names = "uartclk", "apb_pclk"; 368 status = "okay"; 369 }; 370 371#if !TC_DPU_USE_SCMI_CLK 372 dpu_aclk: dpu_aclk { 373 compatible = "fixed-clock"; 374 #clock-cells = <0>; 375 clock-frequency = <LCD_TIMING_CLK>; 376 clock-output-names = "fpga:dpu_aclk"; 377 }; 378 379 dpu_pixel_clk: dpu-pixel-clk { 380 compatible = "fixed-clock"; 381 #clock-cells = <0>; 382 clock-frequency = <LCD_TIMING_CLK>; 383 clock-output-names = "pxclk"; 384 }; 385#endif /* !TC_DPU_USE_SCMI_CLK */ 386 387#if TC_DPU_USE_SIMPLE_PANEL 388 vpanel { 389 compatible = "panel-dpi"; 390 post-init-providers = <&pl0>; 391 port { 392 lcd_in: endpoint { 393 remote-endpoint = <&dp_pl0_out0>; 394 }; 395 }; 396 397 panel-timing { 398 LCD_TIMING; 399 }; 400 }; 401 402#else 403 vencoder { 404 compatible = "drm,virtual-encoder"; 405 port { 406 lcd_in: endpoint { 407 remote-endpoint = <&dp_pl0_out0>; 408 }; 409 }; 410 411 display-timings { 412 timing-panel { 413 LCD_TIMING; 414 }; 415 }; 416 417 }; 418#endif 419 ethernet: ethernet@ETHERNET_ADDR { 420 reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>; 421 interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>; 422 423 reg-io-width = <2>; 424 smsc,irq-push-pull; 425 }; 426 427 bp_clock24mhz: clock24mhz { 428 compatible = "fixed-clock"; 429 #clock-cells = <0>; 430 clock-frequency = <24000000>; 431 clock-output-names = "bp:clock24mhz"; 432 }; 433 434 sysreg: sysreg@SYS_REGS_ADDR { 435 compatible = "arm,vexpress-sysreg"; 436 reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>; 437 gpio-controller; 438 #gpio-cells = <2>; 439 }; 440 441 fixed_3v3: v2m-3v3 { 442 compatible = "regulator-fixed"; 443 regulator-name = "3V3"; 444 regulator-min-microvolt = <3300000>; 445 regulator-max-microvolt = <3300000>; 446 regulator-always-on; 447 }; 448 449 mmci: mmci@MMC_ADDR { 450 compatible = "arm,pl180", "arm,primecell"; 451 reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>; 452 interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>, 453 <GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>; 454 wp-gpios = <&sysreg 1 0>; 455 bus-width = <4>; 456 max-frequency = <25000000>; 457 vmmc-supply = <&fixed_3v3>; 458 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 459 clock-names = "mclk", "apb_pclk"; 460 }; 461 462 gpu_clk: gpu_clk { 463 compatible = "fixed-clock"; 464 #clock-cells = <0>; 465 clock-frequency = <1000000000>; 466 }; 467 468 gpu_core_clk: gpu_core_clk { 469 compatible = "fixed-clock"; 470 #clock-cells = <0>; 471 clock-frequency = <1000000000>; 472 }; 473 474 gpu: gpu@2d000000 { 475 compatible = "arm,mali-midgard"; 476 reg = <0x0 0x2d000000 0x0 0x200000>; 477 clocks = <&gpu_core_clk>; 478 clock-names = "shadercores"; 479#if TC_SCMI_PD_CTRL_EN 480 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 481 scmi-perf-domain = <3>; 482#endif /* TC_SCMI_PD_CTRL_EN */ 483 484 pbha { 485 int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, 486 <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, 487 <12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>, 488 <18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>, 489 <22 0x32>, <24 0x22>, <28 0x32>; 490 propagate-bits = <0x0f>; 491 }; 492 }; 493 494 power_model_simple { 495 /* 496 * Numbers used are irrelevant to Titan, 497 * it helps suppressing the kernel warnings. 498 */ 499 compatible = "arm,mali-simple-power-model"; 500 static-coefficient = <2427750>; 501 dynamic-coefficient = <4687>; 502 ts = <20000 2000 (-20) 2>; 503 thermal-zone = ""; 504 }; 505 506 smmu_600: smmu@2ce00000 { 507 compatible = "arm,smmu-v3"; 508 reg = <0 0x2ce00000 0 0x20000>; 509 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>, 510 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>, 511 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>, 512 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>; 513 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 514 #iommu-cells = <1>; 515 status = "disabled"; 516 }; 517 518 smmu_700: iommu@3f000000 { 519 #iommu-cells = <1>; 520 compatible = "arm,smmu-v3"; 521 reg = <0x0 0x3f000000 0x0 0x5000000>; 522 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>, 523 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>, 524 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>; 525 interrupt-names = "eventq", "cmdq-sync", "gerror"; 526 dma-coherent; 527 status = "disabled"; 528 }; 529 530 smmu_700_dpu: iommu@4002a00000 { 531 #iommu-cells = <1>; 532 compatible = "arm,smmu-v3"; 533 reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>; 534 interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>, 535 <GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>, 536 <GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>; 537 interrupt-names = "eventq", "cmdq-sync", "gerror"; 538 dma-coherent; 539 status = "disabled"; 540 }; 541 542 dp0: display@DPU_ADDR { 543 #address-cells = <1>; 544 #size-cells = <0>; 545 compatible = "arm,mali-d71"; 546 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 547 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>; 548 interrupt-names = "DPU"; 549 DPU_CLK_ATTR1; 550 551 pl0: pipeline@0 { 552 reg = <0>; 553 DPU_CLK_ATTR2; 554 pl_id = <0>; 555 ports { 556 #address-cells = <1>; 557 #size-cells = <0>; 558 port@0 { 559 reg = <0>; 560 dp_pl0_out0: endpoint { 561 remote-endpoint = <&lcd_in>; 562 }; 563 }; 564 }; 565 }; 566 567 pl1: pipeline@1 { 568 reg = <1>; 569 DPU_CLK_ATTR3; 570 pl_id = <1>; 571 ports { 572 #address-cells = <1>; 573 #size-cells = <0>; 574 port@0 { 575 reg = <0>; 576 }; 577 }; 578 }; 579 }; 580 581 /* 582 * L3 cache in the DSU is the Memory System Component (MSC) 583 * The MPAM registers are accessed through utility bus in the DSU 584 */ 585 dsu-msc0 { 586 compatible = "arm,mpam-msc"; 587 reg = <DSU_MPAM_ADDR 0x0 0x2000>; 588 }; 589 590 ete0 { 591 compatible = "arm,embedded-trace-extension"; 592 arm,coresight-loses-context-with-cpu; 593 cpu = <&CPU0>; 594 }; 595 596 ete1 { 597 compatible = "arm,embedded-trace-extension"; 598 arm,coresight-loses-context-with-cpu; 599 cpu = <&CPU1>; 600 }; 601 602 ete2 { 603 compatible = "arm,embedded-trace-extension"; 604 arm,coresight-loses-context-with-cpu; 605 cpu = <&CPU2>; 606 }; 607 608 ete3 { 609 compatible = "arm,embedded-trace-extension"; 610 arm,coresight-loses-context-with-cpu; 611 cpu = <&CPU3>; 612 }; 613 614 ete4 { 615 compatible = "arm,embedded-trace-extension"; 616 arm,coresight-loses-context-with-cpu; 617 cpu = <&CPU4>; 618 }; 619 620 ete5 { 621 compatible = "arm,embedded-trace-extension"; 622 arm,coresight-loses-context-with-cpu; 623 cpu = <&CPU5>; 624 }; 625 626 ete6 { 627 compatible = "arm,embedded-trace-extension"; 628 arm,coresight-loses-context-with-cpu; 629 cpu = <&CPU6>; 630 }; 631 632 ete7 { 633 compatible = "arm,embedded-trace-extension"; 634 arm,coresight-loses-context-with-cpu; 635 cpu = <&CPU7>; 636 }; 637 638 trbe { 639 compatible = "arm,trace-buffer-extension"; 640 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>; 641 }; 642 643 trusty { 644 #size-cells = <0x02>; 645 #address-cells = <0x02>; 646 ranges = <0x00>; 647 compatible = "android,trusty-v1"; 648 649 virtio { 650 compatible = "android,trusty-virtio-v1"; 651 }; 652 653 test { 654 compatible = "android,trusty-test-v1"; 655 }; 656 657 log { 658 compatible = "android,trusty-log-v1"; 659 }; 660 661 irq { 662 ipi-range = <0x08 0x0f 0x08>; 663 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 664 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 665 compatible = "android,trusty-irq-v1"; 666 }; 667 }; 668 669 /* used in U-boot, Linux doesn't care */ 670 arm_ffa { 671 compatible = "arm,ffa"; 672 method = "smc"; 673 }; 674}; 675 676/ { 677 cpus { 678 CPU2:cpu@200 { 679 clocks = <&scmi_dvfs 1>; 680 capacity-dmips-mhz = <MID_CAPACITY>; 681 }; 682 683 CPU3:cpu@300 { 684 clocks = <&scmi_dvfs 1>; 685 capacity-dmips-mhz = <MID_CAPACITY>; 686 }; 687 688 CPU6:cpu@600 { 689 clocks = <&scmi_dvfs 2>; 690 capacity-dmips-mhz = <BIG_CAPACITY>; 691 }; 692 693 CPU7:cpu@700 { 694 clocks = <&scmi_dvfs 2>; 695 capacity-dmips-mhz = <BIG_CAPACITY>; 696 }; 697 }; 698 699 rse_mbox_db_rx: mhu@RSE_MHU_RX_ADDR { 700 compatible = MHU_RX_COMPAT; 701 reg = <0x0 ADDRESSIFY(RSE_MHU_RX_ADDR) 0x0 MHU_OFFSET>; 702 clocks = <&soc_refclk>; 703 clock-names = "apb_pclk"; 704 #mbox-cells = <MHU_MBOX_CELLS>; 705 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 706 interrupt-names = MHU_RX_INT_NAME; 707#if TARGET_FLAVOUR_FPGA 708 status = "disabled"; 709#endif 710 }; 711 712 rse_mbox_db_tx: mhu@RSE_MHU_TX_ADDR { 713 compatible = MHU_TX_COMPAT; 714 reg = <0x0 ADDRESSIFY(RSE_MHU_TX_ADDR) 0x0 MHU_OFFSET>; 715 clocks = <&soc_refclk>; 716 clock-names = "apb_pclk"; 717 #mbox-cells = <MHU_MBOX_CELLS>; 718 interrupt-names = MHU_TX_INT_NAME; 719#if TARGET_FLAVOUR_FPGA 720 status = "disabled"; 721#endif 722 }; 723 724 gic: interrupt-controller@GIC_CTRL_ADDR { 725 ppi-partitions { 726 ppi_partition_little: interrupt-partition-0 { 727 affinity = <&CPU0>, <&CPU1>; 728 }; 729 730 ppi_partition_mid: interrupt-partition-1 { 731 affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; 732 }; 733 734 ppi_partition_big: interrupt-partition-2 { 735 affinity = <&CPU6>, <&CPU7>; 736 }; 737 }; 738 }; 739 740 sram: sram@6000000 { 741 cpu_scp_scmi_p2a: scp-shmem@80 { 742 compatible = "arm,scmi-shmem"; 743 reg = <0x80 0x80>; 744 }; 745 }; 746 747 firmware { 748 scmi { 749 mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; 750 shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; 751 }; 752 753 rse { 754 compatible = "arm,rse"; 755 mbox-names = "tx", "rx"; 756 mboxes = <&rse_mbox_db_tx 0 0 0>, <&rse_mbox_db_rx 0 0 0>; 757#if TARGET_FLAVOUR_FPGA 758 status = "disabled"; 759#endif 760 }; 761 }; 762 763 dsu-pmu { 764 compatible = "arm,dsu-pmu"; 765 cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; 766 }; 767 768 cs-pmu@0 { 769 compatible = "arm,coresight-pmu"; 770 reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; 771 }; 772 773 cs-pmu@1 { 774 compatible = "arm,coresight-pmu"; 775 reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>; 776 }; 777 778 cs-pmu@2 { 779 compatible = "arm,coresight-pmu"; 780 reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>; 781 }; 782 783 cs-pmu@3 { 784 compatible = "arm,coresight-pmu"; 785 reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>; 786 }; 787}; 788