1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp25-clks.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/stm32mp25-resets.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 }; 25 }; 26 27 clocks { 28 clk_hse: clk-hse { 29 #clock-cells = <0>; 30 compatible = "fixed-clock"; 31 clock-frequency = <48000000>; 32 }; 33 34 clk_hsi: clk-hsi { 35 #clock-cells = <0>; 36 compatible = "fixed-clock"; 37 clock-frequency = <64000000>; 38 }; 39 40 clk_lse: clk-lse { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <32768>; 44 }; 45 46 clk_lsi: clk-lsi { 47 #clock-cells = <0>; 48 compatible = "fixed-clock"; 49 clock-frequency = <32000>; 50 }; 51 52 clk_msi: clk-msi { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <16000000>; 56 }; 57 }; 58 59 intc: interrupt-controller@4ac00000 { 60 compatible = "arm,cortex-a7-gic"; 61 #interrupt-cells = <3>; 62 #address-cells = <1>; 63 interrupt-controller; 64 reg = <0x0 0x4ac10000 0x0 0x1000>, 65 <0x0 0x4ac20000 0x0 0x2000>, 66 <0x0 0x4ac40000 0x0 0x2000>, 67 <0x0 0x4ac60000 0x0 0x2000>; 68 }; 69 70 timer { 71 compatible = "arm,armv8-timer"; 72 interrupt-parent = <&intc>; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 77 always-on; 78 }; 79 80 soc@0 { 81 compatible = "simple-bus"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 interrupt-parent = <&intc>; 85 ranges = <0x0 0x0 0x0 0x80000000>; 86 87 rifsc: rifsc@42080000 { 88 compatible = "st,stm32mp25-rifsc"; 89 reg = <0x42080000 0x1000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 93 usart2: serial@400e0000 { 94 compatible = "st,stm32h7-uart"; 95 reg = <0x400e0000 0x400>; 96 clocks = <&rcc CK_KER_USART2>; 97 resets = <&rcc USART2_R>; 98 status = "disabled"; 99 }; 100 101 sdmmc1: mmc@48220000 { 102 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 103 arm,primecell-periphid = <0x00353180>; 104 reg = <0x48220000 0x400>, <0x44230400 0x8>; 105 clocks = <&rcc CK_KER_SDMMC1>; 106 clock-names = "apb_pclk"; 107 resets = <&rcc SDMMC1_R>; 108 cap-sd-highspeed; 109 cap-mmc-highspeed; 110 max-frequency = <120000000>; 111 status = "disabled"; 112 }; 113 114 sdmmc2: mmc@48230000 { 115 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 116 arm,primecell-periphid = <0x00353180>; 117 reg = <0x48230000 0x400>, <0x44230800 0x8>; 118 clocks = <&rcc CK_KER_SDMMC2>; 119 clock-names = "apb_pclk"; 120 resets = <&rcc SDMMC2_R>; 121 cap-sd-highspeed; 122 cap-mmc-highspeed; 123 max-frequency = <120000000>; 124 status = "disabled"; 125 }; 126 }; 127 128 bsec: efuse@44000000 { 129 compatible = "st,stm32mp25-bsec"; 130 reg = <0x44000000 0x400>; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 134 uid_otp: uid-otp@14 { 135 reg = <0x14 0xc>; 136 }; 137 part_number_otp: part-number-otp@24 { 138 reg = <0x24 0x4>; 139 }; 140 nand_otp: otp16@40 { 141 reg = <0x40 0x4>; 142 }; 143 lifecycle2_otp: otp18@48 { 144 reg = <0x48 0x4>; 145 }; 146 nand2_otp: otp20@50 { 147 reg = <0x50 0x4>; 148 }; 149 package_otp: package-otp@1e8 { 150 reg = <0x1e8 0x1>; 151 }; 152 hconf1_otp: otp124@1f0 { 153 reg = <0x1f0 0x4>; 154 }; 155 pkh_otp: otp144@240 { 156 reg = <0x240 0x20>; 157 }; 158 oem_fip_enc_key: otp260@410 { 159 reg = <0x410 0x20>; 160 }; 161 }; 162 163 rcc: rcc@44200000 { 164 compatible = "st,stm32mp25-rcc"; 165 reg = <0x44200000 0x10000>; 166 #clock-cells = <1>; 167 #reset-cells = <1>; 168 }; 169 170 pwr: pwr@44210000 { 171 compatible = "st,stm32mp25-pwr"; 172 reg = <0x44210000 0x400>; 173 174 vddio1: vddio1 { 175 regulator-name = "vddio1"; 176 }; 177 178 vddio2: vddio2 { 179 regulator-name = "vddio2"; 180 }; 181 182 vddio3: vddio3 { 183 regulator-name = "vddio3"; 184 }; 185 186 vddio4: vddio4 { 187 regulator-name = "vddio4"; 188 }; 189 190 vddio: vddio { 191 regulator-name = "vddio"; 192 }; 193 }; 194 195 syscfg: syscon@44230000 { 196 compatible = "st,stm32mp25-syscfg", "syscon"; 197 reg = <0x44230000 0x10000>; 198 }; 199 200 pinctrl: pinctrl@44240000 { 201 #address-cells = <1>; 202 #size-cells = <1>; 203 compatible = "st,stm32mp257-pinctrl"; 204 ranges = <0 0x44240000 0xa0400>; 205 206 gpioa: gpio@44240000 { 207 gpio-controller; 208 #gpio-cells = <2>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 reg = <0x0 0x400>; 212 clocks = <&rcc CK_BUS_GPIOA>; 213 st,bank-name = "GPIOA"; 214 status = "disabled"; 215 }; 216 217 gpiob: gpio@44250000 { 218 gpio-controller; 219 #gpio-cells = <2>; 220 interrupt-controller; 221 #interrupt-cells = <2>; 222 reg = <0x10000 0x400>; 223 clocks = <&rcc CK_BUS_GPIOB>; 224 st,bank-name = "GPIOB"; 225 status = "disabled"; 226 }; 227 228 gpioc: gpio@44260000 { 229 gpio-controller; 230 #gpio-cells = <2>; 231 interrupt-controller; 232 #interrupt-cells = <2>; 233 reg = <0x20000 0x400>; 234 clocks = <&rcc CK_BUS_GPIOC>; 235 st,bank-name = "GPIOC"; 236 status = "disabled"; 237 }; 238 239 gpiod: gpio@44270000 { 240 gpio-controller; 241 #gpio-cells = <2>; 242 interrupt-controller; 243 #interrupt-cells = <2>; 244 reg = <0x30000 0x400>; 245 clocks = <&rcc CK_BUS_GPIOD>; 246 st,bank-name = "GPIOD"; 247 status = "disabled"; 248 }; 249 250 gpioe: gpio@44280000 { 251 gpio-controller; 252 #gpio-cells = <2>; 253 interrupt-controller; 254 #interrupt-cells = <2>; 255 reg = <0x40000 0x400>; 256 clocks = <&rcc CK_BUS_GPIOE>; 257 st,bank-name = "GPIOE"; 258 status = "disabled"; 259 }; 260 261 gpiof: gpio@44290000 { 262 gpio-controller; 263 #gpio-cells = <2>; 264 interrupt-controller; 265 #interrupt-cells = <2>; 266 reg = <0x50000 0x400>; 267 clocks = <&rcc CK_BUS_GPIOF>; 268 st,bank-name = "GPIOF"; 269 status = "disabled"; 270 }; 271 272 gpiog: gpio@442a0000 { 273 gpio-controller; 274 #gpio-cells = <2>; 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 reg = <0x60000 0x400>; 278 clocks = <&rcc CK_BUS_GPIOG>; 279 st,bank-name = "GPIOG"; 280 status = "disabled"; 281 }; 282 283 gpioh: gpio@442b0000 { 284 gpio-controller; 285 #gpio-cells = <2>; 286 interrupt-controller; 287 #interrupt-cells = <2>; 288 reg = <0x70000 0x400>; 289 clocks = <&rcc CK_BUS_GPIOH>; 290 st,bank-name = "GPIOH"; 291 status = "disabled"; 292 }; 293 294 gpioi: gpio@442c0000 { 295 gpio-controller; 296 #gpio-cells = <2>; 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 reg = <0x80000 0x400>; 300 clocks = <&rcc CK_BUS_GPIOI>; 301 st,bank-name = "GPIOI"; 302 status = "disabled"; 303 }; 304 305 gpioj: gpio@442d0000 { 306 gpio-controller; 307 #gpio-cells = <2>; 308 interrupt-controller; 309 #interrupt-cells = <2>; 310 reg = <0x90000 0x400>; 311 clocks = <&rcc CK_BUS_GPIOJ>; 312 st,bank-name = "GPIOJ"; 313 status = "disabled"; 314 }; 315 316 gpiok: gpio@442e0000 { 317 gpio-controller; 318 #gpio-cells = <2>; 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 reg = <0xa0000 0x400>; 322 clocks = <&rcc CK_BUS_GPIOK>; 323 st,bank-name = "GPIOK"; 324 status = "disabled"; 325 }; 326 }; 327 328 pinctrl_z: pinctrl@46200000 { 329 #address-cells = <1>; 330 #size-cells = <1>; 331 compatible = "st,stm32mp257-z-pinctrl"; 332 ranges = <0 0x46200000 0x400>; 333 334 gpioz: gpio@46200000 { 335 gpio-controller; 336 #gpio-cells = <2>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 reg = <0 0x400>; 340 clocks = <&rcc CK_BUS_GPIOZ>; 341 st,bank-name = "GPIOZ"; 342 st,bank-ioport = <11>; 343 status = "disabled"; 344 }; 345 346 }; 347 }; 348}; 349