1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp25-clks.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/stm32mp25-resets.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 }; 25 }; 26 27 clocks { 28 clk_hse: clk-hse { 29 #clock-cells = <0>; 30 compatible = "fixed-clock"; 31 clock-frequency = <48000000>; 32 }; 33 34 clk_hsi: clk-hsi { 35 #clock-cells = <0>; 36 compatible = "fixed-clock"; 37 clock-frequency = <64000000>; 38 }; 39 40 clk_lse: clk-lse { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <32768>; 44 }; 45 46 clk_lsi: clk-lsi { 47 #clock-cells = <0>; 48 compatible = "fixed-clock"; 49 clock-frequency = <32000>; 50 }; 51 52 clk_msi: clk-msi { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <16000000>; 56 }; 57 }; 58 59 intc: interrupt-controller@4ac00000 { 60 compatible = "arm,cortex-a7-gic"; 61 #interrupt-cells = <3>; 62 #address-cells = <1>; 63 interrupt-controller; 64 reg = <0x0 0x4ac10000 0x0 0x1000>, 65 <0x0 0x4ac20000 0x0 0x2000>, 66 <0x0 0x4ac40000 0x0 0x2000>, 67 <0x0 0x4ac60000 0x0 0x2000>; 68 }; 69 70 timer { 71 compatible = "arm,armv8-timer"; 72 interrupt-parent = <&intc>; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 77 always-on; 78 }; 79 80 soc@0 { 81 compatible = "simple-bus"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 interrupt-parent = <&intc>; 85 ranges = <0x0 0x0 0x0 0x80000000>; 86 87 rifsc: rifsc@42080000 { 88 compatible = "st,stm32mp25-rifsc"; 89 reg = <0x42080000 0x1000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 93 usart2: serial@400e0000 { 94 compatible = "st,stm32h7-uart"; 95 reg = <0x400e0000 0x400>; 96 clocks = <&rcc CK_KER_USART2>; 97 resets = <&rcc USART2_R>; 98 status = "disabled"; 99 }; 100 101 usart3: serial@400f0000 { 102 compatible = "st,stm32h7-uart"; 103 reg = <0x400f0000 0x400>; 104 clocks = <&rcc CK_KER_USART3>; 105 resets = <&rcc USART3_R>; 106 status = "disabled"; 107 }; 108 109 uart4: serial@40100000 { 110 compatible = "st,stm32h7-uart"; 111 reg = <0x40100000 0x400>; 112 clocks = <&rcc CK_KER_UART4>; 113 resets = <&rcc UART4_R>; 114 status = "disabled"; 115 }; 116 117 uart5: serial@40110000 { 118 compatible = "st,stm32h7-uart"; 119 reg = <0x40110000 0x400>; 120 clocks = <&rcc CK_KER_UART5>; 121 resets = <&rcc UART5_R>; 122 status = "disabled"; 123 }; 124 125 i2c1: i2c@40120000 { 126 compatible = "st,stm32mp25-i2c"; 127 reg = <0x40120000 0x400>; 128 clocks = <&rcc CK_KER_I2C1>; 129 resets = <&rcc I2C1_R>; 130 status = "disabled"; 131 }; 132 133 i2c2: i2c@40130000 { 134 compatible = "st,stm32mp25-i2c"; 135 reg = <0x40130000 0x400>; 136 clocks = <&rcc CK_KER_I2C2>; 137 resets = <&rcc I2C2_R>; 138 status = "disabled"; 139 }; 140 141 i2c3: i2c@40140000 { 142 compatible = "st,stm32mp25-i2c"; 143 reg = <0x40140000 0x400>; 144 clocks = <&rcc CK_KER_I2C3>; 145 resets = <&rcc I2C3_R>; 146 status = "disabled"; 147 }; 148 149 i2c4: i2c@40150000 { 150 compatible = "st,stm32mp25-i2c"; 151 reg = <0x40150000 0x400>; 152 clocks = <&rcc CK_KER_I2C4>; 153 resets = <&rcc I2C4_R>; 154 status = "disabled"; 155 }; 156 157 i2c5: i2c@40160000 { 158 compatible = "st,stm32mp25-i2c"; 159 reg = <0x40160000 0x400>; 160 clocks = <&rcc CK_KER_I2C5>; 161 resets = <&rcc I2C5_R>; 162 status = "disabled"; 163 }; 164 165 i2c6: i2c@40170000 { 166 compatible = "st,stm32mp25-i2c"; 167 reg = <0x40170000 0x400>; 168 clocks = <&rcc CK_KER_I2C6>; 169 resets = <&rcc I2C6_R>; 170 status = "disabled"; 171 }; 172 173 i2c7: i2c@40180000 { 174 compatible = "st,stm32mp25-i2c"; 175 reg = <0x40180000 0x400>; 176 clocks = <&rcc CK_KER_I2C7>; 177 resets = <&rcc I2C7_R>; 178 status = "disabled"; 179 }; 180 181 usart6: serial@40220000 { 182 compatible = "st,stm32h7-uart"; 183 reg = <0x40220000 0x400>; 184 clocks = <&rcc CK_KER_USART6>; 185 resets = <&rcc USART6_R>; 186 status = "disabled"; 187 }; 188 189 uart9: serial@402c0000 { 190 compatible = "st,stm32h7-uart"; 191 reg = <0x402c0000 0x400>; 192 clocks = <&rcc CK_KER_UART9>; 193 resets = <&rcc UART9_R>; 194 status = "disabled"; 195 }; 196 197 usart1: serial@40330000 { 198 compatible = "st,stm32h7-uart"; 199 reg = <0x40330000 0x400>; 200 clocks = <&rcc CK_KER_USART1>; 201 resets = <&rcc USART1_R>; 202 status = "disabled"; 203 }; 204 205 uart7: serial@40370000 { 206 compatible = "st,stm32h7-uart"; 207 reg = <0x40370000 0x400>; 208 clocks = <&rcc CK_KER_UART7>; 209 resets = <&rcc UART7_R>; 210 status = "disabled"; 211 }; 212 213 uart8: serial@40380000 { 214 compatible = "st,stm32h7-uart"; 215 reg = <0x40380000 0x400>; 216 clocks = <&rcc CK_KER_UART8>; 217 resets = <&rcc UART8_R>; 218 status = "disabled"; 219 }; 220 221 i2c8: i2c@46040000 { 222 compatible = "st,stm32mp25-i2c"; 223 reg = <0x46040000 0x400>; 224 clocks = <&rcc CK_KER_I2C8>; 225 resets = <&rcc I2C8_R>; 226 status = "disabled"; 227 }; 228 229 sdmmc1: mmc@48220000 { 230 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 231 arm,primecell-periphid = <0x00353180>; 232 reg = <0x48220000 0x400>, <0x44230400 0x8>; 233 clocks = <&rcc CK_KER_SDMMC1>; 234 clock-names = "apb_pclk"; 235 resets = <&rcc SDMMC1_R>; 236 cap-sd-highspeed; 237 cap-mmc-highspeed; 238 max-frequency = <120000000>; 239 status = "disabled"; 240 }; 241 242 sdmmc2: mmc@48230000 { 243 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 244 arm,primecell-periphid = <0x00353180>; 245 reg = <0x48230000 0x400>, <0x44230800 0x8>; 246 clocks = <&rcc CK_KER_SDMMC2>; 247 clock-names = "apb_pclk"; 248 resets = <&rcc SDMMC2_R>; 249 cap-sd-highspeed; 250 cap-mmc-highspeed; 251 max-frequency = <120000000>; 252 status = "disabled"; 253 }; 254 }; 255 256 bsec: efuse@44000000 { 257 compatible = "st,stm32mp25-bsec"; 258 reg = <0x44000000 0x400>; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 262 uid_otp: uid-otp@14 { 263 reg = <0x14 0xc>; 264 }; 265 part_number_otp: part-number-otp@24 { 266 reg = <0x24 0x4>; 267 }; 268 nand_otp: otp16@40 { 269 reg = <0x40 0x4>; 270 }; 271 lifecycle2_otp: otp18@48 { 272 reg = <0x48 0x4>; 273 }; 274 nand2_otp: otp20@50 { 275 reg = <0x50 0x4>; 276 }; 277 rev_otp@198 { 278 reg = <0x198 0x4>; 279 }; 280 package_otp: package-otp@1e8 { 281 reg = <0x1e8 0x1>; 282 }; 283 hconf1_otp: otp124@1f0 { 284 reg = <0x1f0 0x4>; 285 }; 286 pkh_otp: otp144@240 { 287 reg = <0x240 0x20>; 288 }; 289 oem_fip_enc_key: otp260@410 { 290 reg = <0x410 0x20>; 291 }; 292 }; 293 294 rcc: rcc@44200000 { 295 compatible = "st,stm32mp25-rcc"; 296 reg = <0x44200000 0x10000>; 297 #clock-cells = <1>; 298 #reset-cells = <1>; 299 }; 300 301 pwr: pwr@44210000 { 302 compatible = "st,stm32mp25-pwr"; 303 reg = <0x44210000 0x400>; 304 305 vddio1: vddio1 { 306 regulator-name = "vddio1"; 307 }; 308 309 vddio2: vddio2 { 310 regulator-name = "vddio2"; 311 }; 312 313 vddio3: vddio3 { 314 regulator-name = "vddio3"; 315 }; 316 317 vddio4: vddio4 { 318 regulator-name = "vddio4"; 319 }; 320 321 vddio: vddio { 322 regulator-name = "vddio"; 323 }; 324 }; 325 326 syscfg: syscon@44230000 { 327 compatible = "st,stm32mp25-syscfg", "syscon"; 328 reg = <0x44230000 0x10000>; 329 }; 330 331 pinctrl: pinctrl@44240000 { 332 #address-cells = <1>; 333 #size-cells = <1>; 334 compatible = "st,stm32mp257-pinctrl"; 335 ranges = <0 0x44240000 0xa0400>; 336 337 gpioa: gpio@44240000 { 338 gpio-controller; 339 #gpio-cells = <2>; 340 interrupt-controller; 341 #interrupt-cells = <2>; 342 reg = <0x0 0x400>; 343 clocks = <&rcc CK_BUS_GPIOA>; 344 st,bank-name = "GPIOA"; 345 status = "disabled"; 346 }; 347 348 gpiob: gpio@44250000 { 349 gpio-controller; 350 #gpio-cells = <2>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 reg = <0x10000 0x400>; 354 clocks = <&rcc CK_BUS_GPIOB>; 355 st,bank-name = "GPIOB"; 356 status = "disabled"; 357 }; 358 359 gpioc: gpio@44260000 { 360 gpio-controller; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 reg = <0x20000 0x400>; 365 clocks = <&rcc CK_BUS_GPIOC>; 366 st,bank-name = "GPIOC"; 367 status = "disabled"; 368 }; 369 370 gpiod: gpio@44270000 { 371 gpio-controller; 372 #gpio-cells = <2>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 reg = <0x30000 0x400>; 376 clocks = <&rcc CK_BUS_GPIOD>; 377 st,bank-name = "GPIOD"; 378 status = "disabled"; 379 }; 380 381 gpioe: gpio@44280000 { 382 gpio-controller; 383 #gpio-cells = <2>; 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 reg = <0x40000 0x400>; 387 clocks = <&rcc CK_BUS_GPIOE>; 388 st,bank-name = "GPIOE"; 389 status = "disabled"; 390 }; 391 392 gpiof: gpio@44290000 { 393 gpio-controller; 394 #gpio-cells = <2>; 395 interrupt-controller; 396 #interrupt-cells = <2>; 397 reg = <0x50000 0x400>; 398 clocks = <&rcc CK_BUS_GPIOF>; 399 st,bank-name = "GPIOF"; 400 status = "disabled"; 401 }; 402 403 gpiog: gpio@442a0000 { 404 gpio-controller; 405 #gpio-cells = <2>; 406 interrupt-controller; 407 #interrupt-cells = <2>; 408 reg = <0x60000 0x400>; 409 clocks = <&rcc CK_BUS_GPIOG>; 410 st,bank-name = "GPIOG"; 411 status = "disabled"; 412 }; 413 414 gpioh: gpio@442b0000 { 415 gpio-controller; 416 #gpio-cells = <2>; 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 reg = <0x70000 0x400>; 420 clocks = <&rcc CK_BUS_GPIOH>; 421 st,bank-name = "GPIOH"; 422 status = "disabled"; 423 }; 424 425 gpioi: gpio@442c0000 { 426 gpio-controller; 427 #gpio-cells = <2>; 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 reg = <0x80000 0x400>; 431 clocks = <&rcc CK_BUS_GPIOI>; 432 st,bank-name = "GPIOI"; 433 status = "disabled"; 434 }; 435 436 gpioj: gpio@442d0000 { 437 gpio-controller; 438 #gpio-cells = <2>; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 reg = <0x90000 0x400>; 442 clocks = <&rcc CK_BUS_GPIOJ>; 443 st,bank-name = "GPIOJ"; 444 status = "disabled"; 445 }; 446 447 gpiok: gpio@442e0000 { 448 gpio-controller; 449 #gpio-cells = <2>; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 reg = <0xa0000 0x400>; 453 clocks = <&rcc CK_BUS_GPIOK>; 454 st,bank-name = "GPIOK"; 455 status = "disabled"; 456 }; 457 }; 458 459 pinctrl_z: pinctrl@46200000 { 460 #address-cells = <1>; 461 #size-cells = <1>; 462 compatible = "st,stm32mp257-z-pinctrl"; 463 ranges = <0 0x46200000 0x400>; 464 465 gpioz: gpio@46200000 { 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupt-controller; 469 #interrupt-cells = <2>; 470 reg = <0 0x400>; 471 clocks = <&rcc CK_BUS_GPIOZ>; 472 st,bank-name = "GPIOZ"; 473 st,bank-ioport = <11>; 474 status = "disabled"; 475 }; 476 477 }; 478 }; 479}; 480