xref: /rk3399_ARM-atf/fdts/stm32mp157a-avenger96.dts (revision cdf3d1a98b751d35c390961b73ee78feff145ff7)
1*cdf3d1a9SManivannan Sadhasivam// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2*cdf3d1a9SManivannan Sadhasivam/*
3*cdf3d1a9SManivannan Sadhasivam * Copyright (C) Arrow Electronics 2019 - All Rights Reserved
4*cdf3d1a9SManivannan Sadhasivam * Author: Botond Kardos <botond.kardos@arroweurope.com>
5*cdf3d1a9SManivannan Sadhasivam *
6*cdf3d1a9SManivannan Sadhasivam * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
7*cdf3d1a9SManivannan Sadhasivam * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
8*cdf3d1a9SManivannan Sadhasivam */
9*cdf3d1a9SManivannan Sadhasivam
10*cdf3d1a9SManivannan Sadhasivam/dts-v1/;
11*cdf3d1a9SManivannan Sadhasivam
12*cdf3d1a9SManivannan Sadhasivam#include "stm32mp157c.dtsi"
13*cdf3d1a9SManivannan Sadhasivam#include "stm32mp157cac-pinctrl.dtsi"
14*cdf3d1a9SManivannan Sadhasivam
15*cdf3d1a9SManivannan Sadhasivam/ {
16*cdf3d1a9SManivannan Sadhasivam	model = "Arrow Electronics STM32MP157A Avenger96 board";
17*cdf3d1a9SManivannan Sadhasivam	compatible = "st,stm32mp157a-avenger96", "st,stm32mp157";
18*cdf3d1a9SManivannan Sadhasivam
19*cdf3d1a9SManivannan Sadhasivam	aliases {
20*cdf3d1a9SManivannan Sadhasivam		serial0 = &uart4;
21*cdf3d1a9SManivannan Sadhasivam	};
22*cdf3d1a9SManivannan Sadhasivam
23*cdf3d1a9SManivannan Sadhasivam	chosen {
24*cdf3d1a9SManivannan Sadhasivam		stdout-path = "serial0:115200n8";
25*cdf3d1a9SManivannan Sadhasivam	};
26*cdf3d1a9SManivannan Sadhasivam
27*cdf3d1a9SManivannan Sadhasivam};
28*cdf3d1a9SManivannan Sadhasivam
29*cdf3d1a9SManivannan Sadhasivam&i2c4 {
30*cdf3d1a9SManivannan Sadhasivam	pinctrl-names = "default";
31*cdf3d1a9SManivannan Sadhasivam	pinctrl-0 = <&i2c4_pins_a>;
32*cdf3d1a9SManivannan Sadhasivam	i2c-scl-rising-time-ns = <185>;
33*cdf3d1a9SManivannan Sadhasivam	i2c-scl-falling-time-ns = <20>;
34*cdf3d1a9SManivannan Sadhasivam	status = "okay";
35*cdf3d1a9SManivannan Sadhasivam
36*cdf3d1a9SManivannan Sadhasivam	pmic: stpmic@33 {
37*cdf3d1a9SManivannan Sadhasivam		compatible = "st,stpmic1";
38*cdf3d1a9SManivannan Sadhasivam		reg = <0x33>;
39*cdf3d1a9SManivannan Sadhasivam		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
40*cdf3d1a9SManivannan Sadhasivam		interrupt-controller;
41*cdf3d1a9SManivannan Sadhasivam		#interrupt-cells = <2>;
42*cdf3d1a9SManivannan Sadhasivam		status = "okay";
43*cdf3d1a9SManivannan Sadhasivam
44*cdf3d1a9SManivannan Sadhasivam		st,main-control-register = <0x04>;
45*cdf3d1a9SManivannan Sadhasivam		st,vin-control-register = <0xc0>;
46*cdf3d1a9SManivannan Sadhasivam		st,usb-control-register = <0x20>;
47*cdf3d1a9SManivannan Sadhasivam
48*cdf3d1a9SManivannan Sadhasivam		regulators {
49*cdf3d1a9SManivannan Sadhasivam			compatible = "st,stpmic1-regulators";
50*cdf3d1a9SManivannan Sadhasivam
51*cdf3d1a9SManivannan Sadhasivam			ldo1-supply = <&v3v3>;
52*cdf3d1a9SManivannan Sadhasivam			ldo2-supply = <&v3v3>;
53*cdf3d1a9SManivannan Sadhasivam			ldo3-supply = <&vdd_ddr>;
54*cdf3d1a9SManivannan Sadhasivam			ldo5-supply = <&v3v3>;
55*cdf3d1a9SManivannan Sadhasivam			ldo6-supply = <&v3v3>;
56*cdf3d1a9SManivannan Sadhasivam
57*cdf3d1a9SManivannan Sadhasivam			vddcore: buck1 {
58*cdf3d1a9SManivannan Sadhasivam				regulator-name = "vddcore";
59*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <1200000>;
60*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <1350000>;
61*cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
62*cdf3d1a9SManivannan Sadhasivam				regulator-initial-mode = <0>;
63*cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
64*cdf3d1a9SManivannan Sadhasivam			};
65*cdf3d1a9SManivannan Sadhasivam
66*cdf3d1a9SManivannan Sadhasivam			vdd_ddr: buck2 {
67*cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdd_ddr";
68*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <1350000>;
69*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <1350000>;
70*cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
71*cdf3d1a9SManivannan Sadhasivam				regulator-initial-mode = <0>;
72*cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
73*cdf3d1a9SManivannan Sadhasivam			};
74*cdf3d1a9SManivannan Sadhasivam
75*cdf3d1a9SManivannan Sadhasivam			vdd: buck3 {
76*cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdd";
77*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <3300000>;
78*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <3300000>;
79*cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
80*cdf3d1a9SManivannan Sadhasivam				st,mask-reset;
81*cdf3d1a9SManivannan Sadhasivam				regulator-initial-mode = <0>;
82*cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
83*cdf3d1a9SManivannan Sadhasivam			};
84*cdf3d1a9SManivannan Sadhasivam
85*cdf3d1a9SManivannan Sadhasivam			v3v3: buck4 {
86*cdf3d1a9SManivannan Sadhasivam				regulator-name = "v3v3";
87*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <3300000>;
88*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <3300000>;
89*cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
90*cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
91*cdf3d1a9SManivannan Sadhasivam				regulator-initial-mode = <0>;
92*cdf3d1a9SManivannan Sadhasivam			};
93*cdf3d1a9SManivannan Sadhasivam
94*cdf3d1a9SManivannan Sadhasivam			vdda: ldo1 {
95*cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdda";
96*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <2900000>;
97*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <2900000>;
98*cdf3d1a9SManivannan Sadhasivam			};
99*cdf3d1a9SManivannan Sadhasivam
100*cdf3d1a9SManivannan Sadhasivam			v2v8: ldo2 {
101*cdf3d1a9SManivannan Sadhasivam				regulator-name = "v2v8";
102*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <2800000>;
103*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <2800000>;
104*cdf3d1a9SManivannan Sadhasivam			};
105*cdf3d1a9SManivannan Sadhasivam
106*cdf3d1a9SManivannan Sadhasivam			vtt_ddr: ldo3 {
107*cdf3d1a9SManivannan Sadhasivam				regulator-name = "vtt_ddr";
108*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <500000>;
109*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <750000>;
110*cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
111*cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
112*cdf3d1a9SManivannan Sadhasivam			};
113*cdf3d1a9SManivannan Sadhasivam
114*cdf3d1a9SManivannan Sadhasivam			vdd_usb: ldo4 {
115*cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdd_usb";
116*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <3300000>;
117*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <3300000>;
118*cdf3d1a9SManivannan Sadhasivam			};
119*cdf3d1a9SManivannan Sadhasivam
120*cdf3d1a9SManivannan Sadhasivam			vdd_sd: ldo5 {
121*cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdd_sd";
122*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <2900000>;
123*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <2900000>;
124*cdf3d1a9SManivannan Sadhasivam				regulator-boot-on;
125*cdf3d1a9SManivannan Sadhasivam			};
126*cdf3d1a9SManivannan Sadhasivam
127*cdf3d1a9SManivannan Sadhasivam			v1v8: ldo6 {
128*cdf3d1a9SManivannan Sadhasivam				regulator-name = "v1v8";
129*cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <1800000>;
130*cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <1800000>;
131*cdf3d1a9SManivannan Sadhasivam			};
132*cdf3d1a9SManivannan Sadhasivam
133*cdf3d1a9SManivannan Sadhasivam			vref_ddr: vref_ddr {
134*cdf3d1a9SManivannan Sadhasivam				regulator-name = "vref_ddr";
135*cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
136*cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
137*cdf3d1a9SManivannan Sadhasivam			};
138*cdf3d1a9SManivannan Sadhasivam		};
139*cdf3d1a9SManivannan Sadhasivam	};
140*cdf3d1a9SManivannan Sadhasivam};
141*cdf3d1a9SManivannan Sadhasivam
142*cdf3d1a9SManivannan Sadhasivam&iwdg2 {
143*cdf3d1a9SManivannan Sadhasivam	timeout-sec = <32>;
144*cdf3d1a9SManivannan Sadhasivam	status = "okay";
145*cdf3d1a9SManivannan Sadhasivam};
146*cdf3d1a9SManivannan Sadhasivam
147*cdf3d1a9SManivannan Sadhasivam&rng1 {
148*cdf3d1a9SManivannan Sadhasivam	status = "okay";
149*cdf3d1a9SManivannan Sadhasivam};
150*cdf3d1a9SManivannan Sadhasivam
151*cdf3d1a9SManivannan Sadhasivam&rtc {
152*cdf3d1a9SManivannan Sadhasivam	status = "okay";
153*cdf3d1a9SManivannan Sadhasivam};
154*cdf3d1a9SManivannan Sadhasivam
155*cdf3d1a9SManivannan Sadhasivam&sdmmc1 {
156*cdf3d1a9SManivannan Sadhasivam	pinctrl-names = "default";
157*cdf3d1a9SManivannan Sadhasivam	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
158*cdf3d1a9SManivannan Sadhasivam	broken-cd;
159*cdf3d1a9SManivannan Sadhasivam	st,sig-dir;
160*cdf3d1a9SManivannan Sadhasivam	st,neg-edge;
161*cdf3d1a9SManivannan Sadhasivam	st,use-ckin;
162*cdf3d1a9SManivannan Sadhasivam	bus-width = <4>;
163*cdf3d1a9SManivannan Sadhasivam	vmmc-supply = <&vdda>;
164*cdf3d1a9SManivannan Sadhasivam	status = "okay";
165*cdf3d1a9SManivannan Sadhasivam};
166*cdf3d1a9SManivannan Sadhasivam
167*cdf3d1a9SManivannan Sadhasivam&uart4 {
168*cdf3d1a9SManivannan Sadhasivam	pinctrl-names = "default";
169*cdf3d1a9SManivannan Sadhasivam	pinctrl-0 = <&uart4_pins_b>;
170*cdf3d1a9SManivannan Sadhasivam	status = "okay";
171*cdf3d1a9SManivannan Sadhasivam};
172*cdf3d1a9SManivannan Sadhasivam
173*cdf3d1a9SManivannan Sadhasivam/* ATF Specific */
174*cdf3d1a9SManivannan Sadhasivam#include <dt-bindings/clock/stm32mp1-clksrc.h>
175*cdf3d1a9SManivannan Sadhasivam#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
176*cdf3d1a9SManivannan Sadhasivam#include "stm32mp157c-security.dtsi"
177*cdf3d1a9SManivannan Sadhasivam
178*cdf3d1a9SManivannan Sadhasivam/ {
179*cdf3d1a9SManivannan Sadhasivam	aliases {
180*cdf3d1a9SManivannan Sadhasivam		gpio0 = &gpioa;
181*cdf3d1a9SManivannan Sadhasivam		gpio1 = &gpiob;
182*cdf3d1a9SManivannan Sadhasivam		gpio2 = &gpioc;
183*cdf3d1a9SManivannan Sadhasivam		gpio3 = &gpiod;
184*cdf3d1a9SManivannan Sadhasivam		gpio4 = &gpioe;
185*cdf3d1a9SManivannan Sadhasivam		gpio5 = &gpiof;
186*cdf3d1a9SManivannan Sadhasivam		gpio6 = &gpiog;
187*cdf3d1a9SManivannan Sadhasivam		gpio7 = &gpioh;
188*cdf3d1a9SManivannan Sadhasivam		gpio8 = &gpioi;
189*cdf3d1a9SManivannan Sadhasivam		gpio25 = &gpioz;
190*cdf3d1a9SManivannan Sadhasivam		i2c3 = &i2c4;
191*cdf3d1a9SManivannan Sadhasivam	};
192*cdf3d1a9SManivannan Sadhasivam};
193*cdf3d1a9SManivannan Sadhasivam
194*cdf3d1a9SManivannan Sadhasivam/* CLOCK init */
195*cdf3d1a9SManivannan Sadhasivam&rcc {
196*cdf3d1a9SManivannan Sadhasivam	secure-status = "disabled";
197*cdf3d1a9SManivannan Sadhasivam	st,clksrc = <
198*cdf3d1a9SManivannan Sadhasivam		CLK_MPU_PLL1P
199*cdf3d1a9SManivannan Sadhasivam		CLK_AXI_PLL2P
200*cdf3d1a9SManivannan Sadhasivam		CLK_MCU_PLL3P
201*cdf3d1a9SManivannan Sadhasivam		CLK_PLL12_HSE
202*cdf3d1a9SManivannan Sadhasivam		CLK_PLL3_HSE
203*cdf3d1a9SManivannan Sadhasivam		CLK_PLL4_HSE
204*cdf3d1a9SManivannan Sadhasivam		CLK_RTC_LSE
205*cdf3d1a9SManivannan Sadhasivam		CLK_MCO1_DISABLED
206*cdf3d1a9SManivannan Sadhasivam		CLK_MCO2_DISABLED
207*cdf3d1a9SManivannan Sadhasivam	>;
208*cdf3d1a9SManivannan Sadhasivam
209*cdf3d1a9SManivannan Sadhasivam	st,clkdiv = <
210*cdf3d1a9SManivannan Sadhasivam		1 /*MPU*/
211*cdf3d1a9SManivannan Sadhasivam		0 /*AXI*/
212*cdf3d1a9SManivannan Sadhasivam		0 /*MCU*/
213*cdf3d1a9SManivannan Sadhasivam		1 /*APB1*/
214*cdf3d1a9SManivannan Sadhasivam		1 /*APB2*/
215*cdf3d1a9SManivannan Sadhasivam		1 /*APB3*/
216*cdf3d1a9SManivannan Sadhasivam		1 /*APB4*/
217*cdf3d1a9SManivannan Sadhasivam		2 /*APB5*/
218*cdf3d1a9SManivannan Sadhasivam		23 /*RTC*/
219*cdf3d1a9SManivannan Sadhasivam		0 /*MCO1*/
220*cdf3d1a9SManivannan Sadhasivam		0 /*MCO2*/
221*cdf3d1a9SManivannan Sadhasivam	>;
222*cdf3d1a9SManivannan Sadhasivam
223*cdf3d1a9SManivannan Sadhasivam	st,pkcs = <
224*cdf3d1a9SManivannan Sadhasivam		CLK_CKPER_HSE
225*cdf3d1a9SManivannan Sadhasivam		CLK_FMC_ACLK
226*cdf3d1a9SManivannan Sadhasivam		CLK_QSPI_ACLK
227*cdf3d1a9SManivannan Sadhasivam		CLK_ETH_DISABLED
228*cdf3d1a9SManivannan Sadhasivam		CLK_SDMMC12_PLL4P
229*cdf3d1a9SManivannan Sadhasivam		CLK_DSI_DSIPLL
230*cdf3d1a9SManivannan Sadhasivam		CLK_STGEN_HSE
231*cdf3d1a9SManivannan Sadhasivam		CLK_USBPHY_HSE
232*cdf3d1a9SManivannan Sadhasivam		CLK_SPI2S1_PLL3Q
233*cdf3d1a9SManivannan Sadhasivam		CLK_SPI2S23_PLL3Q
234*cdf3d1a9SManivannan Sadhasivam		CLK_SPI45_HSI
235*cdf3d1a9SManivannan Sadhasivam		CLK_SPI6_HSI
236*cdf3d1a9SManivannan Sadhasivam		CLK_I2C46_HSI
237*cdf3d1a9SManivannan Sadhasivam		CLK_SDMMC3_PLL4P
238*cdf3d1a9SManivannan Sadhasivam		CLK_USBO_USBPHY
239*cdf3d1a9SManivannan Sadhasivam		CLK_ADC_CKPER
240*cdf3d1a9SManivannan Sadhasivam		CLK_CEC_LSE
241*cdf3d1a9SManivannan Sadhasivam		CLK_I2C12_HSI
242*cdf3d1a9SManivannan Sadhasivam		CLK_I2C35_HSI
243*cdf3d1a9SManivannan Sadhasivam		CLK_UART1_HSI
244*cdf3d1a9SManivannan Sadhasivam		CLK_UART24_HSI
245*cdf3d1a9SManivannan Sadhasivam		CLK_UART35_HSI
246*cdf3d1a9SManivannan Sadhasivam		CLK_UART6_HSI
247*cdf3d1a9SManivannan Sadhasivam		CLK_UART78_HSI
248*cdf3d1a9SManivannan Sadhasivam		CLK_SPDIF_PLL4P
249*cdf3d1a9SManivannan Sadhasivam		CLK_FDCAN_PLL4Q
250*cdf3d1a9SManivannan Sadhasivam		CLK_SAI1_PLL3Q
251*cdf3d1a9SManivannan Sadhasivam		CLK_SAI2_PLL3Q
252*cdf3d1a9SManivannan Sadhasivam		CLK_SAI3_PLL3Q
253*cdf3d1a9SManivannan Sadhasivam		CLK_SAI4_PLL3Q
254*cdf3d1a9SManivannan Sadhasivam		CLK_RNG1_LSI
255*cdf3d1a9SManivannan Sadhasivam		CLK_RNG2_LSI
256*cdf3d1a9SManivannan Sadhasivam		CLK_LPTIM1_PCLK1
257*cdf3d1a9SManivannan Sadhasivam		CLK_LPTIM23_PCLK3
258*cdf3d1a9SManivannan Sadhasivam		CLK_LPTIM45_LSE
259*cdf3d1a9SManivannan Sadhasivam	>;
260*cdf3d1a9SManivannan Sadhasivam
261*cdf3d1a9SManivannan Sadhasivam	/* VCO = 1300.0 MHz => P = 650 (CPU) */
262*cdf3d1a9SManivannan Sadhasivam	pll1: st,pll@0 {
263*cdf3d1a9SManivannan Sadhasivam		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
264*cdf3d1a9SManivannan Sadhasivam		frac = < 0x800 >;
265*cdf3d1a9SManivannan Sadhasivam	};
266*cdf3d1a9SManivannan Sadhasivam
267*cdf3d1a9SManivannan Sadhasivam	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
268*cdf3d1a9SManivannan Sadhasivam	pll2: st,pll@1 {
269*cdf3d1a9SManivannan Sadhasivam		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
270*cdf3d1a9SManivannan Sadhasivam		frac = < 0x1400 >;
271*cdf3d1a9SManivannan Sadhasivam	};
272*cdf3d1a9SManivannan Sadhasivam
273*cdf3d1a9SManivannan Sadhasivam	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
274*cdf3d1a9SManivannan Sadhasivam	pll3: st,pll@2 {
275*cdf3d1a9SManivannan Sadhasivam		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
276*cdf3d1a9SManivannan Sadhasivam		frac = < 0x1a04 >;
277*cdf3d1a9SManivannan Sadhasivam	};
278*cdf3d1a9SManivannan Sadhasivam
279*cdf3d1a9SManivannan Sadhasivam	/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
280*cdf3d1a9SManivannan Sadhasivam	pll4: st,pll@3 {
281*cdf3d1a9SManivannan Sadhasivam		cfg = < 1 39 3 11 4 PQR(1,1,1) >;
282*cdf3d1a9SManivannan Sadhasivam	};
283*cdf3d1a9SManivannan Sadhasivam};
284