1cdf3d1a9SManivannan Sadhasivam// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2cdf3d1a9SManivannan Sadhasivam/* 3cdf3d1a9SManivannan Sadhasivam * Copyright (C) Arrow Electronics 2019 - All Rights Reserved 4cdf3d1a9SManivannan Sadhasivam * Author: Botond Kardos <botond.kardos@arroweurope.com> 5cdf3d1a9SManivannan Sadhasivam * 6cdf3d1a9SManivannan Sadhasivam * Copyright (C) Linaro Ltd 2019 - All Rights Reserved 7cdf3d1a9SManivannan Sadhasivam * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 8cdf3d1a9SManivannan Sadhasivam */ 9cdf3d1a9SManivannan Sadhasivam 10cdf3d1a9SManivannan Sadhasivam/dts-v1/; 11cdf3d1a9SManivannan Sadhasivam 12cdf3d1a9SManivannan Sadhasivam#include "stm32mp157c.dtsi" 13cdf3d1a9SManivannan Sadhasivam#include "stm32mp157cac-pinctrl.dtsi" 14cdf3d1a9SManivannan Sadhasivam 15cdf3d1a9SManivannan Sadhasivam/ { 16cdf3d1a9SManivannan Sadhasivam model = "Arrow Electronics STM32MP157A Avenger96 board"; 17cdf3d1a9SManivannan Sadhasivam compatible = "st,stm32mp157a-avenger96", "st,stm32mp157"; 18cdf3d1a9SManivannan Sadhasivam 19cdf3d1a9SManivannan Sadhasivam aliases { 20cdf3d1a9SManivannan Sadhasivam serial0 = &uart4; 21cdf3d1a9SManivannan Sadhasivam }; 22cdf3d1a9SManivannan Sadhasivam 23cdf3d1a9SManivannan Sadhasivam chosen { 24cdf3d1a9SManivannan Sadhasivam stdout-path = "serial0:115200n8"; 25cdf3d1a9SManivannan Sadhasivam }; 26cdf3d1a9SManivannan Sadhasivam 27cdf3d1a9SManivannan Sadhasivam}; 28cdf3d1a9SManivannan Sadhasivam 29cdf3d1a9SManivannan Sadhasivam&i2c4 { 30cdf3d1a9SManivannan Sadhasivam pinctrl-names = "default"; 31cdf3d1a9SManivannan Sadhasivam pinctrl-0 = <&i2c4_pins_a>; 32cdf3d1a9SManivannan Sadhasivam i2c-scl-rising-time-ns = <185>; 33cdf3d1a9SManivannan Sadhasivam i2c-scl-falling-time-ns = <20>; 34cdf3d1a9SManivannan Sadhasivam status = "okay"; 35cdf3d1a9SManivannan Sadhasivam 36cdf3d1a9SManivannan Sadhasivam pmic: stpmic@33 { 37cdf3d1a9SManivannan Sadhasivam compatible = "st,stpmic1"; 38cdf3d1a9SManivannan Sadhasivam reg = <0x33>; 39cdf3d1a9SManivannan Sadhasivam interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 40cdf3d1a9SManivannan Sadhasivam interrupt-controller; 41cdf3d1a9SManivannan Sadhasivam #interrupt-cells = <2>; 42cdf3d1a9SManivannan Sadhasivam status = "okay"; 43cdf3d1a9SManivannan Sadhasivam 44cdf3d1a9SManivannan Sadhasivam st,main-control-register = <0x04>; 45cdf3d1a9SManivannan Sadhasivam st,vin-control-register = <0xc0>; 46cdf3d1a9SManivannan Sadhasivam st,usb-control-register = <0x20>; 47cdf3d1a9SManivannan Sadhasivam 48cdf3d1a9SManivannan Sadhasivam regulators { 49cdf3d1a9SManivannan Sadhasivam compatible = "st,stpmic1-regulators"; 50cdf3d1a9SManivannan Sadhasivam 51cdf3d1a9SManivannan Sadhasivam ldo1-supply = <&v3v3>; 52cdf3d1a9SManivannan Sadhasivam ldo2-supply = <&v3v3>; 53cdf3d1a9SManivannan Sadhasivam ldo3-supply = <&vdd_ddr>; 54cdf3d1a9SManivannan Sadhasivam ldo5-supply = <&v3v3>; 55cdf3d1a9SManivannan Sadhasivam ldo6-supply = <&v3v3>; 56cdf3d1a9SManivannan Sadhasivam 57cdf3d1a9SManivannan Sadhasivam vddcore: buck1 { 58cdf3d1a9SManivannan Sadhasivam regulator-name = "vddcore"; 59cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <1200000>; 60cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <1350000>; 61cdf3d1a9SManivannan Sadhasivam regulator-always-on; 62cdf3d1a9SManivannan Sadhasivam regulator-initial-mode = <0>; 63cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 64cdf3d1a9SManivannan Sadhasivam }; 65cdf3d1a9SManivannan Sadhasivam 66cdf3d1a9SManivannan Sadhasivam vdd_ddr: buck2 { 67cdf3d1a9SManivannan Sadhasivam regulator-name = "vdd_ddr"; 68cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <1350000>; 69cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <1350000>; 70cdf3d1a9SManivannan Sadhasivam regulator-always-on; 71cdf3d1a9SManivannan Sadhasivam regulator-initial-mode = <0>; 72cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 73cdf3d1a9SManivannan Sadhasivam }; 74cdf3d1a9SManivannan Sadhasivam 75cdf3d1a9SManivannan Sadhasivam vdd: buck3 { 76cdf3d1a9SManivannan Sadhasivam regulator-name = "vdd"; 77cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <3300000>; 78cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <3300000>; 79cdf3d1a9SManivannan Sadhasivam regulator-always-on; 80cdf3d1a9SManivannan Sadhasivam st,mask-reset; 81cdf3d1a9SManivannan Sadhasivam regulator-initial-mode = <0>; 82cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 83cdf3d1a9SManivannan Sadhasivam }; 84cdf3d1a9SManivannan Sadhasivam 85cdf3d1a9SManivannan Sadhasivam v3v3: buck4 { 86cdf3d1a9SManivannan Sadhasivam regulator-name = "v3v3"; 87cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <3300000>; 88cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <3300000>; 89cdf3d1a9SManivannan Sadhasivam regulator-always-on; 90cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 91cdf3d1a9SManivannan Sadhasivam regulator-initial-mode = <0>; 92cdf3d1a9SManivannan Sadhasivam }; 93cdf3d1a9SManivannan Sadhasivam 94cdf3d1a9SManivannan Sadhasivam vdda: ldo1 { 95cdf3d1a9SManivannan Sadhasivam regulator-name = "vdda"; 96cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <2900000>; 97cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <2900000>; 98cdf3d1a9SManivannan Sadhasivam }; 99cdf3d1a9SManivannan Sadhasivam 100cdf3d1a9SManivannan Sadhasivam v2v8: ldo2 { 101cdf3d1a9SManivannan Sadhasivam regulator-name = "v2v8"; 102cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <2800000>; 103cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <2800000>; 104cdf3d1a9SManivannan Sadhasivam }; 105cdf3d1a9SManivannan Sadhasivam 106cdf3d1a9SManivannan Sadhasivam vtt_ddr: ldo3 { 107cdf3d1a9SManivannan Sadhasivam regulator-name = "vtt_ddr"; 108cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <500000>; 109cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <750000>; 110cdf3d1a9SManivannan Sadhasivam regulator-always-on; 111cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 112cdf3d1a9SManivannan Sadhasivam }; 113cdf3d1a9SManivannan Sadhasivam 114cdf3d1a9SManivannan Sadhasivam vdd_usb: ldo4 { 115cdf3d1a9SManivannan Sadhasivam regulator-name = "vdd_usb"; 116cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <3300000>; 117cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <3300000>; 118cdf3d1a9SManivannan Sadhasivam }; 119cdf3d1a9SManivannan Sadhasivam 120cdf3d1a9SManivannan Sadhasivam vdd_sd: ldo5 { 121cdf3d1a9SManivannan Sadhasivam regulator-name = "vdd_sd"; 122cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <2900000>; 123cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <2900000>; 124cdf3d1a9SManivannan Sadhasivam regulator-boot-on; 125cdf3d1a9SManivannan Sadhasivam }; 126cdf3d1a9SManivannan Sadhasivam 127cdf3d1a9SManivannan Sadhasivam v1v8: ldo6 { 128cdf3d1a9SManivannan Sadhasivam regulator-name = "v1v8"; 129cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <1800000>; 130cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <1800000>; 131cdf3d1a9SManivannan Sadhasivam }; 132cdf3d1a9SManivannan Sadhasivam 133cdf3d1a9SManivannan Sadhasivam vref_ddr: vref_ddr { 134cdf3d1a9SManivannan Sadhasivam regulator-name = "vref_ddr"; 135cdf3d1a9SManivannan Sadhasivam regulator-always-on; 136cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 137cdf3d1a9SManivannan Sadhasivam }; 138cdf3d1a9SManivannan Sadhasivam }; 139cdf3d1a9SManivannan Sadhasivam }; 140cdf3d1a9SManivannan Sadhasivam}; 141cdf3d1a9SManivannan Sadhasivam 142cdf3d1a9SManivannan Sadhasivam&iwdg2 { 143cdf3d1a9SManivannan Sadhasivam timeout-sec = <32>; 144cdf3d1a9SManivannan Sadhasivam status = "okay"; 145cdf3d1a9SManivannan Sadhasivam}; 146cdf3d1a9SManivannan Sadhasivam 147cdf3d1a9SManivannan Sadhasivam&rng1 { 148cdf3d1a9SManivannan Sadhasivam status = "okay"; 149cdf3d1a9SManivannan Sadhasivam}; 150cdf3d1a9SManivannan Sadhasivam 151cdf3d1a9SManivannan Sadhasivam&rtc { 152cdf3d1a9SManivannan Sadhasivam status = "okay"; 153cdf3d1a9SManivannan Sadhasivam}; 154cdf3d1a9SManivannan Sadhasivam 155cdf3d1a9SManivannan Sadhasivam&sdmmc1 { 156cdf3d1a9SManivannan Sadhasivam pinctrl-names = "default"; 157cdf3d1a9SManivannan Sadhasivam pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 158cdf3d1a9SManivannan Sadhasivam broken-cd; 159cdf3d1a9SManivannan Sadhasivam st,sig-dir; 160cdf3d1a9SManivannan Sadhasivam st,neg-edge; 161cdf3d1a9SManivannan Sadhasivam st,use-ckin; 162cdf3d1a9SManivannan Sadhasivam bus-width = <4>; 163cdf3d1a9SManivannan Sadhasivam vmmc-supply = <&vdda>; 164cdf3d1a9SManivannan Sadhasivam status = "okay"; 165cdf3d1a9SManivannan Sadhasivam}; 166cdf3d1a9SManivannan Sadhasivam 167cdf3d1a9SManivannan Sadhasivam&uart4 { 168cdf3d1a9SManivannan Sadhasivam pinctrl-names = "default"; 169cdf3d1a9SManivannan Sadhasivam pinctrl-0 = <&uart4_pins_b>; 170cdf3d1a9SManivannan Sadhasivam status = "okay"; 171cdf3d1a9SManivannan Sadhasivam}; 172cdf3d1a9SManivannan Sadhasivam 173cdf3d1a9SManivannan Sadhasivam/* ATF Specific */ 174cdf3d1a9SManivannan Sadhasivam#include <dt-bindings/clock/stm32mp1-clksrc.h> 175cdf3d1a9SManivannan Sadhasivam#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 176cdf3d1a9SManivannan Sadhasivam#include "stm32mp157c-security.dtsi" 177cdf3d1a9SManivannan Sadhasivam 178cdf3d1a9SManivannan Sadhasivam/ { 179cdf3d1a9SManivannan Sadhasivam aliases { 180cdf3d1a9SManivannan Sadhasivam gpio0 = &gpioa; 181cdf3d1a9SManivannan Sadhasivam gpio1 = &gpiob; 182cdf3d1a9SManivannan Sadhasivam gpio2 = &gpioc; 183cdf3d1a9SManivannan Sadhasivam gpio3 = &gpiod; 184cdf3d1a9SManivannan Sadhasivam gpio4 = &gpioe; 185cdf3d1a9SManivannan Sadhasivam gpio5 = &gpiof; 186cdf3d1a9SManivannan Sadhasivam gpio6 = &gpiog; 187cdf3d1a9SManivannan Sadhasivam gpio7 = &gpioh; 188cdf3d1a9SManivannan Sadhasivam gpio8 = &gpioi; 189cdf3d1a9SManivannan Sadhasivam gpio25 = &gpioz; 190cdf3d1a9SManivannan Sadhasivam i2c3 = &i2c4; 191cdf3d1a9SManivannan Sadhasivam }; 192cdf3d1a9SManivannan Sadhasivam}; 193cdf3d1a9SManivannan Sadhasivam 194cdf3d1a9SManivannan Sadhasivam/* CLOCK init */ 195cdf3d1a9SManivannan Sadhasivam&rcc { 196cdf3d1a9SManivannan Sadhasivam secure-status = "disabled"; 197cdf3d1a9SManivannan Sadhasivam st,clksrc = < 198cdf3d1a9SManivannan Sadhasivam CLK_MPU_PLL1P 199cdf3d1a9SManivannan Sadhasivam CLK_AXI_PLL2P 200cdf3d1a9SManivannan Sadhasivam CLK_MCU_PLL3P 201cdf3d1a9SManivannan Sadhasivam CLK_PLL12_HSE 202cdf3d1a9SManivannan Sadhasivam CLK_PLL3_HSE 203cdf3d1a9SManivannan Sadhasivam CLK_PLL4_HSE 204cdf3d1a9SManivannan Sadhasivam CLK_RTC_LSE 205cdf3d1a9SManivannan Sadhasivam CLK_MCO1_DISABLED 206cdf3d1a9SManivannan Sadhasivam CLK_MCO2_DISABLED 207cdf3d1a9SManivannan Sadhasivam >; 208cdf3d1a9SManivannan Sadhasivam 209cdf3d1a9SManivannan Sadhasivam st,clkdiv = < 210cdf3d1a9SManivannan Sadhasivam 1 /*MPU*/ 211cdf3d1a9SManivannan Sadhasivam 0 /*AXI*/ 212cdf3d1a9SManivannan Sadhasivam 0 /*MCU*/ 213cdf3d1a9SManivannan Sadhasivam 1 /*APB1*/ 214cdf3d1a9SManivannan Sadhasivam 1 /*APB2*/ 215cdf3d1a9SManivannan Sadhasivam 1 /*APB3*/ 216cdf3d1a9SManivannan Sadhasivam 1 /*APB4*/ 217cdf3d1a9SManivannan Sadhasivam 2 /*APB5*/ 218cdf3d1a9SManivannan Sadhasivam 23 /*RTC*/ 219cdf3d1a9SManivannan Sadhasivam 0 /*MCO1*/ 220cdf3d1a9SManivannan Sadhasivam 0 /*MCO2*/ 221cdf3d1a9SManivannan Sadhasivam >; 222cdf3d1a9SManivannan Sadhasivam 223cdf3d1a9SManivannan Sadhasivam st,pkcs = < 224cdf3d1a9SManivannan Sadhasivam CLK_CKPER_HSE 225cdf3d1a9SManivannan Sadhasivam CLK_FMC_ACLK 226cdf3d1a9SManivannan Sadhasivam CLK_QSPI_ACLK 227cdf3d1a9SManivannan Sadhasivam CLK_ETH_DISABLED 228cdf3d1a9SManivannan Sadhasivam CLK_SDMMC12_PLL4P 229cdf3d1a9SManivannan Sadhasivam CLK_DSI_DSIPLL 230cdf3d1a9SManivannan Sadhasivam CLK_STGEN_HSE 231cdf3d1a9SManivannan Sadhasivam CLK_USBPHY_HSE 232cdf3d1a9SManivannan Sadhasivam CLK_SPI2S1_PLL3Q 233cdf3d1a9SManivannan Sadhasivam CLK_SPI2S23_PLL3Q 234cdf3d1a9SManivannan Sadhasivam CLK_SPI45_HSI 235cdf3d1a9SManivannan Sadhasivam CLK_SPI6_HSI 236cdf3d1a9SManivannan Sadhasivam CLK_I2C46_HSI 237cdf3d1a9SManivannan Sadhasivam CLK_SDMMC3_PLL4P 238cdf3d1a9SManivannan Sadhasivam CLK_USBO_USBPHY 239cdf3d1a9SManivannan Sadhasivam CLK_ADC_CKPER 240cdf3d1a9SManivannan Sadhasivam CLK_CEC_LSE 241cdf3d1a9SManivannan Sadhasivam CLK_I2C12_HSI 242cdf3d1a9SManivannan Sadhasivam CLK_I2C35_HSI 243cdf3d1a9SManivannan Sadhasivam CLK_UART1_HSI 244cdf3d1a9SManivannan Sadhasivam CLK_UART24_HSI 245cdf3d1a9SManivannan Sadhasivam CLK_UART35_HSI 246cdf3d1a9SManivannan Sadhasivam CLK_UART6_HSI 247cdf3d1a9SManivannan Sadhasivam CLK_UART78_HSI 248cdf3d1a9SManivannan Sadhasivam CLK_SPDIF_PLL4P 249*2dc9fe70SAntonio Borneo CLK_FDCAN_PLL4R 250cdf3d1a9SManivannan Sadhasivam CLK_SAI1_PLL3Q 251cdf3d1a9SManivannan Sadhasivam CLK_SAI2_PLL3Q 252cdf3d1a9SManivannan Sadhasivam CLK_SAI3_PLL3Q 253cdf3d1a9SManivannan Sadhasivam CLK_SAI4_PLL3Q 254cdf3d1a9SManivannan Sadhasivam CLK_RNG1_LSI 255cdf3d1a9SManivannan Sadhasivam CLK_RNG2_LSI 256cdf3d1a9SManivannan Sadhasivam CLK_LPTIM1_PCLK1 257cdf3d1a9SManivannan Sadhasivam CLK_LPTIM23_PCLK3 258cdf3d1a9SManivannan Sadhasivam CLK_LPTIM45_LSE 259cdf3d1a9SManivannan Sadhasivam >; 260cdf3d1a9SManivannan Sadhasivam 261cdf3d1a9SManivannan Sadhasivam /* VCO = 1300.0 MHz => P = 650 (CPU) */ 262cdf3d1a9SManivannan Sadhasivam pll1: st,pll@0 { 263cdf3d1a9SManivannan Sadhasivam cfg = < 2 80 0 0 0 PQR(1,0,0) >; 264cdf3d1a9SManivannan Sadhasivam frac = < 0x800 >; 265cdf3d1a9SManivannan Sadhasivam }; 266cdf3d1a9SManivannan Sadhasivam 267cdf3d1a9SManivannan Sadhasivam /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 268cdf3d1a9SManivannan Sadhasivam pll2: st,pll@1 { 269cdf3d1a9SManivannan Sadhasivam cfg = < 2 65 1 0 0 PQR(1,1,1) >; 270cdf3d1a9SManivannan Sadhasivam frac = < 0x1400 >; 271cdf3d1a9SManivannan Sadhasivam }; 272cdf3d1a9SManivannan Sadhasivam 273cdf3d1a9SManivannan Sadhasivam /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 274cdf3d1a9SManivannan Sadhasivam pll3: st,pll@2 { 275cdf3d1a9SManivannan Sadhasivam cfg = < 1 33 1 16 36 PQR(1,1,1) >; 276cdf3d1a9SManivannan Sadhasivam frac = < 0x1a04 >; 277cdf3d1a9SManivannan Sadhasivam }; 278cdf3d1a9SManivannan Sadhasivam 279cdf3d1a9SManivannan Sadhasivam /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ 280cdf3d1a9SManivannan Sadhasivam pll4: st,pll@3 { 281cdf3d1a9SManivannan Sadhasivam cfg = < 1 39 3 11 4 PQR(1,1,1) >; 282cdf3d1a9SManivannan Sadhasivam }; 283cdf3d1a9SManivannan Sadhasivam}; 284