1cdf3d1a9SManivannan Sadhasivam// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2cdf3d1a9SManivannan Sadhasivam/* 3cdf3d1a9SManivannan Sadhasivam * Copyright (C) Arrow Electronics 2019 - All Rights Reserved 4cdf3d1a9SManivannan Sadhasivam * Author: Botond Kardos <botond.kardos@arroweurope.com> 5cdf3d1a9SManivannan Sadhasivam * 6cdf3d1a9SManivannan Sadhasivam * Copyright (C) Linaro Ltd 2019 - All Rights Reserved 7cdf3d1a9SManivannan Sadhasivam * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 8cdf3d1a9SManivannan Sadhasivam */ 9cdf3d1a9SManivannan Sadhasivam 10cdf3d1a9SManivannan Sadhasivam/dts-v1/; 11cdf3d1a9SManivannan Sadhasivam 12*277d6af5SYann Gautier#include "stm32mp157.dtsi" 13*277d6af5SYann Gautier#include "stm32mp15-pinctrl.dtsi" 14*277d6af5SYann Gautier#include "stm32mp15xxac-pinctrl.dtsi" 15*277d6af5SYann Gautier#include <dt-bindings/clock/stm32mp1-clksrc.h> 16*277d6af5SYann Gautier#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 17cdf3d1a9SManivannan Sadhasivam 18cdf3d1a9SManivannan Sadhasivam/ { 19cdf3d1a9SManivannan Sadhasivam model = "Arrow Electronics STM32MP157A Avenger96 board"; 20*277d6af5SYann Gautier compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; 21cdf3d1a9SManivannan Sadhasivam 22cdf3d1a9SManivannan Sadhasivam aliases { 23*277d6af5SYann Gautier mmc0 = &sdmmc1; 24cdf3d1a9SManivannan Sadhasivam serial0 = &uart4; 25*277d6af5SYann Gautier serial1 = &uart7; 26cdf3d1a9SManivannan Sadhasivam }; 27cdf3d1a9SManivannan Sadhasivam 28cdf3d1a9SManivannan Sadhasivam chosen { 29cdf3d1a9SManivannan Sadhasivam stdout-path = "serial0:115200n8"; 30cdf3d1a9SManivannan Sadhasivam }; 31cdf3d1a9SManivannan Sadhasivam 32*277d6af5SYann Gautier memory@c0000000 { 33*277d6af5SYann Gautier device_type = "memory"; 34*277d6af5SYann Gautier reg = <0xc0000000 0x40000000>; 35*277d6af5SYann Gautier }; 36cdf3d1a9SManivannan Sadhasivam}; 37cdf3d1a9SManivannan Sadhasivam 38cdf3d1a9SManivannan Sadhasivam&i2c4 { 39cdf3d1a9SManivannan Sadhasivam pinctrl-names = "default"; 40cdf3d1a9SManivannan Sadhasivam pinctrl-0 = <&i2c4_pins_a>; 41cdf3d1a9SManivannan Sadhasivam i2c-scl-rising-time-ns = <185>; 42cdf3d1a9SManivannan Sadhasivam i2c-scl-falling-time-ns = <20>; 43cdf3d1a9SManivannan Sadhasivam status = "okay"; 44cdf3d1a9SManivannan Sadhasivam 45cdf3d1a9SManivannan Sadhasivam pmic: stpmic@33 { 46cdf3d1a9SManivannan Sadhasivam compatible = "st,stpmic1"; 47cdf3d1a9SManivannan Sadhasivam reg = <0x33>; 48cdf3d1a9SManivannan Sadhasivam interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 49cdf3d1a9SManivannan Sadhasivam interrupt-controller; 50cdf3d1a9SManivannan Sadhasivam #interrupt-cells = <2>; 51cdf3d1a9SManivannan Sadhasivam status = "okay"; 52cdf3d1a9SManivannan Sadhasivam 53cdf3d1a9SManivannan Sadhasivam st,main-control-register = <0x04>; 54cdf3d1a9SManivannan Sadhasivam st,vin-control-register = <0xc0>; 55*277d6af5SYann Gautier st,usb-control-register = <0x30>; 56cdf3d1a9SManivannan Sadhasivam 57cdf3d1a9SManivannan Sadhasivam regulators { 58cdf3d1a9SManivannan Sadhasivam compatible = "st,stpmic1-regulators"; 59cdf3d1a9SManivannan Sadhasivam ldo1-supply = <&v3v3>; 60cdf3d1a9SManivannan Sadhasivam ldo2-supply = <&v3v3>; 61cdf3d1a9SManivannan Sadhasivam ldo3-supply = <&vdd_ddr>; 62cdf3d1a9SManivannan Sadhasivam ldo5-supply = <&v3v3>; 63cdf3d1a9SManivannan Sadhasivam ldo6-supply = <&v3v3>; 64*277d6af5SYann Gautier pwr_sw1-supply = <&bst_out>; 65*277d6af5SYann Gautier pwr_sw2-supply = <&bst_out>; 66cdf3d1a9SManivannan Sadhasivam 67cdf3d1a9SManivannan Sadhasivam vddcore: buck1 { 68cdf3d1a9SManivannan Sadhasivam regulator-name = "vddcore"; 69cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <1200000>; 70cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <1350000>; 71cdf3d1a9SManivannan Sadhasivam regulator-always-on; 72cdf3d1a9SManivannan Sadhasivam regulator-initial-mode = <0>; 73cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 74cdf3d1a9SManivannan Sadhasivam }; 75cdf3d1a9SManivannan Sadhasivam 76cdf3d1a9SManivannan Sadhasivam vdd_ddr: buck2 { 77cdf3d1a9SManivannan Sadhasivam regulator-name = "vdd_ddr"; 78cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <1350000>; 79cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <1350000>; 80cdf3d1a9SManivannan Sadhasivam regulator-always-on; 81cdf3d1a9SManivannan Sadhasivam regulator-initial-mode = <0>; 82cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 83cdf3d1a9SManivannan Sadhasivam }; 84cdf3d1a9SManivannan Sadhasivam 85cdf3d1a9SManivannan Sadhasivam vdd: buck3 { 86cdf3d1a9SManivannan Sadhasivam regulator-name = "vdd"; 87cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <3300000>; 88cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <3300000>; 89cdf3d1a9SManivannan Sadhasivam regulator-always-on; 90cdf3d1a9SManivannan Sadhasivam st,mask-reset; 91cdf3d1a9SManivannan Sadhasivam regulator-initial-mode = <0>; 92cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 93cdf3d1a9SManivannan Sadhasivam }; 94cdf3d1a9SManivannan Sadhasivam 95cdf3d1a9SManivannan Sadhasivam v3v3: buck4 { 96cdf3d1a9SManivannan Sadhasivam regulator-name = "v3v3"; 97cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <3300000>; 98cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <3300000>; 99cdf3d1a9SManivannan Sadhasivam regulator-always-on; 100cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 101cdf3d1a9SManivannan Sadhasivam regulator-initial-mode = <0>; 102cdf3d1a9SManivannan Sadhasivam }; 103cdf3d1a9SManivannan Sadhasivam 104cdf3d1a9SManivannan Sadhasivam vdda: ldo1 { 105cdf3d1a9SManivannan Sadhasivam regulator-name = "vdda"; 106cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <2900000>; 107cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <2900000>; 108cdf3d1a9SManivannan Sadhasivam }; 109cdf3d1a9SManivannan Sadhasivam 110cdf3d1a9SManivannan Sadhasivam v2v8: ldo2 { 111cdf3d1a9SManivannan Sadhasivam regulator-name = "v2v8"; 112cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <2800000>; 113cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <2800000>; 114cdf3d1a9SManivannan Sadhasivam }; 115cdf3d1a9SManivannan Sadhasivam 116cdf3d1a9SManivannan Sadhasivam vtt_ddr: ldo3 { 117cdf3d1a9SManivannan Sadhasivam regulator-name = "vtt_ddr"; 118cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <500000>; 119cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <750000>; 120cdf3d1a9SManivannan Sadhasivam regulator-always-on; 121cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 122cdf3d1a9SManivannan Sadhasivam }; 123cdf3d1a9SManivannan Sadhasivam 124cdf3d1a9SManivannan Sadhasivam vdd_usb: ldo4 { 125cdf3d1a9SManivannan Sadhasivam regulator-name = "vdd_usb"; 126cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <3300000>; 127cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <3300000>; 128cdf3d1a9SManivannan Sadhasivam }; 129cdf3d1a9SManivannan Sadhasivam 130cdf3d1a9SManivannan Sadhasivam vdd_sd: ldo5 { 131cdf3d1a9SManivannan Sadhasivam regulator-name = "vdd_sd"; 132cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <2900000>; 133cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <2900000>; 134cdf3d1a9SManivannan Sadhasivam regulator-boot-on; 135cdf3d1a9SManivannan Sadhasivam }; 136cdf3d1a9SManivannan Sadhasivam 137cdf3d1a9SManivannan Sadhasivam v1v8: ldo6 { 138cdf3d1a9SManivannan Sadhasivam regulator-name = "v1v8"; 139cdf3d1a9SManivannan Sadhasivam regulator-min-microvolt = <1800000>; 140cdf3d1a9SManivannan Sadhasivam regulator-max-microvolt = <1800000>; 141cdf3d1a9SManivannan Sadhasivam }; 142cdf3d1a9SManivannan Sadhasivam 143cdf3d1a9SManivannan Sadhasivam vref_ddr: vref_ddr { 144cdf3d1a9SManivannan Sadhasivam regulator-name = "vref_ddr"; 145cdf3d1a9SManivannan Sadhasivam regulator-always-on; 146cdf3d1a9SManivannan Sadhasivam regulator-over-current-protection; 147cdf3d1a9SManivannan Sadhasivam }; 148*277d6af5SYann Gautier 149*277d6af5SYann Gautier bst_out: boost { 150*277d6af5SYann Gautier regulator-name = "bst_out"; 151*277d6af5SYann Gautier }; 152*277d6af5SYann Gautier 153*277d6af5SYann Gautier vbus_otg: pwr_sw1 { 154*277d6af5SYann Gautier regulator-name = "vbus_otg"; 155*277d6af5SYann Gautier }; 156*277d6af5SYann Gautier 157*277d6af5SYann Gautier vbus_sw: pwr_sw2 { 158*277d6af5SYann Gautier regulator-name = "vbus_sw"; 159*277d6af5SYann Gautier regulator-active-discharge = <1>; 160*277d6af5SYann Gautier }; 161cdf3d1a9SManivannan Sadhasivam }; 162cdf3d1a9SManivannan Sadhasivam }; 163cdf3d1a9SManivannan Sadhasivam}; 164cdf3d1a9SManivannan Sadhasivam 165cdf3d1a9SManivannan Sadhasivam&iwdg2 { 166cdf3d1a9SManivannan Sadhasivam timeout-sec = <32>; 167cdf3d1a9SManivannan Sadhasivam status = "okay"; 168*277d6af5SYann Gautier secure-status = "okay"; 169cdf3d1a9SManivannan Sadhasivam}; 170cdf3d1a9SManivannan Sadhasivam 171*277d6af5SYann Gautier&pwr_regulators { 172*277d6af5SYann Gautier vdd-supply = <&vdd>; 173*277d6af5SYann Gautier vdd_3v3_usbfs-supply = <&vdd_usb>; 174cdf3d1a9SManivannan Sadhasivam}; 175cdf3d1a9SManivannan Sadhasivam 176cdf3d1a9SManivannan Sadhasivam&rcc { 177cdf3d1a9SManivannan Sadhasivam secure-status = "disabled"; 178cdf3d1a9SManivannan Sadhasivam st,clksrc = < 179cdf3d1a9SManivannan Sadhasivam CLK_MPU_PLL1P 180cdf3d1a9SManivannan Sadhasivam CLK_AXI_PLL2P 181cdf3d1a9SManivannan Sadhasivam CLK_MCU_PLL3P 182cdf3d1a9SManivannan Sadhasivam CLK_PLL12_HSE 183cdf3d1a9SManivannan Sadhasivam CLK_PLL3_HSE 184cdf3d1a9SManivannan Sadhasivam CLK_PLL4_HSE 185cdf3d1a9SManivannan Sadhasivam CLK_RTC_LSE 186cdf3d1a9SManivannan Sadhasivam CLK_MCO1_DISABLED 187cdf3d1a9SManivannan Sadhasivam CLK_MCO2_DISABLED 188cdf3d1a9SManivannan Sadhasivam >; 189cdf3d1a9SManivannan Sadhasivam 190cdf3d1a9SManivannan Sadhasivam st,clkdiv = < 191cdf3d1a9SManivannan Sadhasivam 1 /*MPU*/ 192cdf3d1a9SManivannan Sadhasivam 0 /*AXI*/ 193cdf3d1a9SManivannan Sadhasivam 0 /*MCU*/ 194cdf3d1a9SManivannan Sadhasivam 1 /*APB1*/ 195cdf3d1a9SManivannan Sadhasivam 1 /*APB2*/ 196cdf3d1a9SManivannan Sadhasivam 1 /*APB3*/ 197cdf3d1a9SManivannan Sadhasivam 1 /*APB4*/ 198cdf3d1a9SManivannan Sadhasivam 2 /*APB5*/ 199cdf3d1a9SManivannan Sadhasivam 23 /*RTC*/ 200cdf3d1a9SManivannan Sadhasivam 0 /*MCO1*/ 201cdf3d1a9SManivannan Sadhasivam 0 /*MCO2*/ 202cdf3d1a9SManivannan Sadhasivam >; 203cdf3d1a9SManivannan Sadhasivam 204cdf3d1a9SManivannan Sadhasivam st,pkcs = < 205cdf3d1a9SManivannan Sadhasivam CLK_CKPER_HSE 206cdf3d1a9SManivannan Sadhasivam CLK_FMC_ACLK 207cdf3d1a9SManivannan Sadhasivam CLK_QSPI_ACLK 208cdf3d1a9SManivannan Sadhasivam CLK_ETH_DISABLED 209cdf3d1a9SManivannan Sadhasivam CLK_SDMMC12_PLL4P 210cdf3d1a9SManivannan Sadhasivam CLK_DSI_DSIPLL 211cdf3d1a9SManivannan Sadhasivam CLK_STGEN_HSE 212cdf3d1a9SManivannan Sadhasivam CLK_USBPHY_HSE 213cdf3d1a9SManivannan Sadhasivam CLK_SPI2S1_PLL3Q 214cdf3d1a9SManivannan Sadhasivam CLK_SPI2S23_PLL3Q 215cdf3d1a9SManivannan Sadhasivam CLK_SPI45_HSI 216cdf3d1a9SManivannan Sadhasivam CLK_SPI6_HSI 217cdf3d1a9SManivannan Sadhasivam CLK_I2C46_HSI 218cdf3d1a9SManivannan Sadhasivam CLK_SDMMC3_PLL4P 219cdf3d1a9SManivannan Sadhasivam CLK_USBO_USBPHY 220cdf3d1a9SManivannan Sadhasivam CLK_ADC_CKPER 221cdf3d1a9SManivannan Sadhasivam CLK_CEC_LSE 222cdf3d1a9SManivannan Sadhasivam CLK_I2C12_HSI 223cdf3d1a9SManivannan Sadhasivam CLK_I2C35_HSI 224cdf3d1a9SManivannan Sadhasivam CLK_UART1_HSI 225cdf3d1a9SManivannan Sadhasivam CLK_UART24_HSI 226cdf3d1a9SManivannan Sadhasivam CLK_UART35_HSI 227cdf3d1a9SManivannan Sadhasivam CLK_UART6_HSI 228cdf3d1a9SManivannan Sadhasivam CLK_UART78_HSI 229cdf3d1a9SManivannan Sadhasivam CLK_SPDIF_PLL4P 2302dc9fe70SAntonio Borneo CLK_FDCAN_PLL4R 231cdf3d1a9SManivannan Sadhasivam CLK_SAI1_PLL3Q 232cdf3d1a9SManivannan Sadhasivam CLK_SAI2_PLL3Q 233cdf3d1a9SManivannan Sadhasivam CLK_SAI3_PLL3Q 234cdf3d1a9SManivannan Sadhasivam CLK_SAI4_PLL3Q 235cdf3d1a9SManivannan Sadhasivam CLK_RNG1_LSI 236cdf3d1a9SManivannan Sadhasivam CLK_RNG2_LSI 237cdf3d1a9SManivannan Sadhasivam CLK_LPTIM1_PCLK1 238cdf3d1a9SManivannan Sadhasivam CLK_LPTIM23_PCLK3 239cdf3d1a9SManivannan Sadhasivam CLK_LPTIM45_LSE 240cdf3d1a9SManivannan Sadhasivam >; 241cdf3d1a9SManivannan Sadhasivam 242cdf3d1a9SManivannan Sadhasivam /* VCO = 1300.0 MHz => P = 650 (CPU) */ 243cdf3d1a9SManivannan Sadhasivam pll1: st,pll@0 { 244*277d6af5SYann Gautier compatible = "st,stm32mp1-pll"; 245*277d6af5SYann Gautier reg = <0>; 246cdf3d1a9SManivannan Sadhasivam cfg = <2 80 0 0 0 PQR(1,0,0)>; 247cdf3d1a9SManivannan Sadhasivam frac = <0x800>; 248cdf3d1a9SManivannan Sadhasivam }; 249cdf3d1a9SManivannan Sadhasivam 250cdf3d1a9SManivannan Sadhasivam /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 251cdf3d1a9SManivannan Sadhasivam pll2: st,pll@1 { 252*277d6af5SYann Gautier compatible = "st,stm32mp1-pll"; 253*277d6af5SYann Gautier reg = <1>; 254cdf3d1a9SManivannan Sadhasivam cfg = <2 65 1 0 0 PQR(1,1,1)>; 255cdf3d1a9SManivannan Sadhasivam frac = <0x1400>; 256cdf3d1a9SManivannan Sadhasivam }; 257cdf3d1a9SManivannan Sadhasivam 258cdf3d1a9SManivannan Sadhasivam /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 259cdf3d1a9SManivannan Sadhasivam pll3: st,pll@2 { 260*277d6af5SYann Gautier compatible = "st,stm32mp1-pll"; 261*277d6af5SYann Gautier reg = <2>; 262cdf3d1a9SManivannan Sadhasivam cfg = <1 33 1 16 36 PQR(1,1,1)>; 263cdf3d1a9SManivannan Sadhasivam frac = <0x1a04>; 264cdf3d1a9SManivannan Sadhasivam }; 265cdf3d1a9SManivannan Sadhasivam 266cdf3d1a9SManivannan Sadhasivam /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ 267cdf3d1a9SManivannan Sadhasivam pll4: st,pll@3 { 268*277d6af5SYann Gautier compatible = "st,stm32mp1-pll"; 269*277d6af5SYann Gautier reg = <3>; 270cdf3d1a9SManivannan Sadhasivam cfg = <1 39 3 11 4 PQR(1,1,1)>; 271cdf3d1a9SManivannan Sadhasivam }; 272cdf3d1a9SManivannan Sadhasivam}; 273*277d6af5SYann Gautier 274*277d6af5SYann Gautier&rng1 { 275*277d6af5SYann Gautier status = "okay"; 276*277d6af5SYann Gautier}; 277*277d6af5SYann Gautier 278*277d6af5SYann Gautier&rtc { 279*277d6af5SYann Gautier status = "okay"; 280*277d6af5SYann Gautier}; 281*277d6af5SYann Gautier 282*277d6af5SYann Gautier&sdmmc1 { 283*277d6af5SYann Gautier pinctrl-names = "default"; 284*277d6af5SYann Gautier pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 285*277d6af5SYann Gautier st,sig-dir; 286*277d6af5SYann Gautier st,neg-edge; 287*277d6af5SYann Gautier st,use-ckin; 288*277d6af5SYann Gautier bus-width = <4>; 289*277d6af5SYann Gautier vmmc-supply = <&vdd_sd>; 290*277d6af5SYann Gautier status = "okay"; 291*277d6af5SYann Gautier}; 292*277d6af5SYann Gautier 293*277d6af5SYann Gautier&uart4 { 294*277d6af5SYann Gautier /* On Low speed expansion header */ 295*277d6af5SYann Gautier label = "LS-UART1"; 296*277d6af5SYann Gautier pinctrl-names = "default"; 297*277d6af5SYann Gautier pinctrl-0 = <&uart4_pins_b>; 298*277d6af5SYann Gautier status = "okay"; 299*277d6af5SYann Gautier}; 300*277d6af5SYann Gautier 301*277d6af5SYann Gautier&uart7 { 302*277d6af5SYann Gautier /* On Low speed expansion header */ 303*277d6af5SYann Gautier label = "LS-UART0"; 304*277d6af5SYann Gautier pinctrl-names = "default"; 305*277d6af5SYann Gautier pinctrl-0 = <&uart7_pins_a>; 306*277d6af5SYann Gautier status = "okay"; 307*277d6af5SYann Gautier}; 308