1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8#include "morello.dtsi" 9#include "morello-coresight.dtsi" 10 11/ { 12 model = "Arm Morello System Development Platform"; 13 14 chosen { 15 stdout-path = "serial0:115200n8"; 16 }; 17 18 reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 secure-firmware@ff000000 { 24 reg = <0 0xff000000 0 0x01000000>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <2>; 31 #size-cells = <0>; 32 cpu0: cpu0@0 { 33 compatible = "arm,armv8"; 34 reg = <0x0 0x0>; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 clocks = <&scmi_dvfs 0>; 38 operating-points = < 39 /* kHz uV */ 40 2600000 925000 41 2400000 875000 42 2200000 825000 43 2000000 775000 44 1800000 750000 45 >; 46 #cooling-cells = <2>; 47 }; 48 cpu1: cpu1@100 { 49 compatible = "arm,armv8"; 50 reg = <0x0 0x100>; 51 device_type = "cpu"; 52 enable-method = "psci"; 53 clocks = <&scmi_dvfs 0>; 54 operating-points = < 55 /* kHz uV */ 56 2600000 925000 57 2400000 875000 58 2200000 825000 59 2000000 775000 60 1800000 750000 61 >; 62 #cooling-cells = <2>; 63 }; 64 cpu2: cpu2@10000 { 65 compatible = "arm,armv8"; 66 reg = <0x0 0x10000>; 67 device_type = "cpu"; 68 enable-method = "psci"; 69 clocks = <&scmi_dvfs 1>; 70 operating-points = < 71 /* kHz uV */ 72 2600000 925000 73 2400000 875000 74 2200000 825000 75 2000000 775000 76 1800000 750000 77 >; 78 #cooling-cells = <2>; 79 }; 80 cpu3: cpu3@10100 { 81 compatible = "arm,armv8"; 82 reg = <0x0 0x10100>; 83 device_type = "cpu"; 84 enable-method = "psci"; 85 clocks = <&scmi_dvfs 1>; 86 operating-points = < 87 /* kHz uV */ 88 2600000 925000 89 2400000 875000 90 2200000 825000 91 2000000 775000 92 1800000 750000 93 >; 94 #cooling-cells = <2>; 95 }; 96 }; 97 98 /* The first bank of memory, memory map is actually provided by UEFI. */ 99 memory@80000000 { 100 device_type = "memory"; 101 /* [0x80000000-0xffffffff] */ 102 reg = <0x00000000 0x80000000 0x0 0x7F000000>; 103 }; 104 105 memory@8080000000 { 106 device_type = "memory"; 107 /* [0x8080000000-0x83f7ffffff] */ 108 reg = <0x00000080 0x80000000 0x3 0x78000000>; 109 }; 110 111 smmu_pcie: iommu@4f400000 { 112 compatible = "arm,smmu-v3"; 113 reg = <0 0x4f400000 0 0x40000>; 114 interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, 115 <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, 116 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 117 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 118 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 119 msi-parent = <&its2 0>; 120 #iommu-cells = <1>; 121 dma-coherent; 122 }; 123 124 pcie_ctlr: pcie@28c0000000 { 125 compatible = "pci-host-ecam-generic"; 126 device_type = "pci"; 127 reg = <0x28 0xC0000000 0 0x10000000>; 128 bus-range = <0 255>; 129 linux,pci-domain = <0>; 130 #address-cells = <3>; 131 #size-cells = <2>; 132 dma-coherent; 133 ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>, 134 <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>, 135 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>; 136 #interrupt-cells = <1>; 137 interrupt-map-mask = <0 0 0 7>; 138 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, 139 <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, 140 <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, 141 <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; 142 msi-map = <0 &its_pcie 0 0x10000>; 143 iommu-map = <0 &smmu_pcie 0 0x10000>; 144 status = "okay"; 145 }; 146 147 smmu_ccix: iommu@4f000000 { 148 compatible = "arm,smmu-v3"; 149 reg = <0 0x4f000000 0 0x40000>; 150 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 151 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>, 152 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 153 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 154 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 155 msi-parent = <&its1 0>; 156 #iommu-cells = <1>; 157 dma-coherent; 158 }; 159 160 ccix_pcie_ctlr: pcie@4fc0000000 { 161 compatible = "pci-host-ecam-generic"; 162 device_type = "pci"; 163 reg = <0x4F 0xC0000000 0 0x10000000>; 164 bus-range = <0 255>; 165 linux,pci-domain = <1>; 166 #address-cells = <3>; 167 #size-cells = <2>; 168 dma-coherent; 169 ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>, 170 <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>, 171 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>; 172 #interrupt-cells = <1>; 173 interrupt-map-mask = <0 0 0 7>; 174 interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, 175 <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, 176 <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, 177 <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; 178 msi-map = <0 &its_ccix 0 0x10000>; 179 iommu-map = <0 &smmu_ccix 0 0x10000>; 180 status = "okay"; 181 }; 182 183 smmu_dp: iommu@2ce00000 { 184 compatible = "arm,smmu-v3"; 185 reg = <0 0x2ce00000 0 0x40000>; 186 interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 187 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 188 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; 189 interrupt-names = "eventq", "gerror", "cmdq-sync"; 190 #iommu-cells = <1>; 191 }; 192 193 dp0: display@2cc00000 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "arm,mali-d32", "arm,mali-d71"; 197 reg = <0 0x2cc00000 0 0x20000>; 198 interrupts = <0 69 4>; 199 interrupt-names = "DPU"; 200 clocks = <&dpu_aclk>; 201 clock-names = "aclk"; 202 iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, 203 <&smmu_dp 8>; 204 205 pl0: pipeline@0 { 206 reg = <0>; 207 clocks = <&scmi_clk 1>; 208 clock-names = "pxclk"; 209 pl_id = <0>; 210 ports { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 port@0 { 214 reg = <0>; 215 dp_pl0_out0: endpoint { 216 remote-endpoint = <&tda998x_0_input>; 217 }; 218 }; 219 }; 220 }; 221 }; 222 223 i2c@1c0f0000 { 224 compatible = "cdns,i2c-r1p14"; 225 reg = <0x0 0x1c0f0000 0x0 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 clock-frequency = <100000>; 229 i2c-sda-hold-time-ns = <500>; 230 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&dpu_aclk>; 232 233 hdmi_tx: hdmi-transmitter@70 { 234 compatible = "nxp,tda998x"; 235 reg = <0x70>; 236 video-ports = <0x234501>; 237 #sound-dai-cells = <0>; 238 audio-ports = <2 0x03>; 239 port { 240 tda998x_0_input: endpoint { 241 remote-endpoint = <&dp_pl0_out0>; 242 }; 243 }; 244 }; 245 }; 246 247 dpu_aclk: dpu_aclk { 248 /* 77.1 MHz derived from 24 MHz reference clock */ 249 compatible = "fixed-clock"; 250 #clock-cells = <0>; 251 clock-frequency = <350000000>; 252 clock-output-names = "aclk"; 253 }; 254 255 gpu@2d000000 { 256 compatible = "arm,mali-bifrost"; 257 reg = <0x0 0x2d000000 0x0 0x4000>; 258 interrupts = 259 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-names = 263 "gpu", 264 "job", 265 "mmu"; 266 clocks = <&clk_gpu>; 267 clock-names = "clk_mali"; 268 status = "okay"; 269 }; 270 271 clk_gpu: clk_gpu { 272 compatible = "fixed-clock"; 273 #clock-cells = <0>; 274 clock-frequency = <650000000>; 275 clock-output-names = "clk_mali"; 276 }; 277 278 firmware { 279 scmi { 280 compatible = "arm,scmi"; 281 mbox-names = "tx", "rx"; 282 mboxes = <&mailbox 1 0>, <&mailbox 1 1>; 283 shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 scmi_dvfs: protocol@13 { 287 reg = <0x13>; 288 #clock-cells = <1>; 289 }; 290 scmi_clk: protocol@14 { 291 reg = <0x14>; 292 #clock-cells = <1>; 293 }; 294 scmi_sensor: protocol@15 { 295 reg = <0x15>; 296 #thermal-sensor-cells = <1>; 297 }; 298 }; 299 }; 300 301 thermal-zones { 302 clus0-thermal { 303 polling-delay-passive = <200>; /* ms */ 304 polling-delay = <1000>; /* ms */ 305 306 thermal-sensors = <&scmi_sensor 0>; 307 308 trips { 309 clus0_alarm: clus0-alarm { 310 temperature = <85000>; /* millicelsius */ 311 hysteresis = <1000>; /* millicelsius */ 312 type = "passive"; 313 }; 314 clus0_shutdown: clus0-shutdown { 315 temperature = <90000>; /* millicelsius */ 316 hysteresis = <0>; /* millicelsius */ 317 type = "critical"; 318 }; 319 }; 320 321 cooling-maps { 322 map0 { 323 trip = <&clus0_alarm>; 324 cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; 325 }; 326 }; 327 }; 328 clus1-thermal { 329 polling-delay-passive = <200>; /* ms */ 330 polling-delay = <1000>; /* ms */ 331 332 thermal-sensors = <&scmi_sensor 1>; 333 trips { 334 clus1_alarm: clus1-alarm { 335 temperature = <85000>; /* millicelsius */ 336 hysteresis = <1000>; /* millicelsius */ 337 type = "passive"; 338 }; 339 clus1_shutdown: clus1-shutdown { 340 temperature = <90000>; /* millicelsius */ 341 hysteresis = <0>; /* millicelsius */ 342 type = "critical"; 343 }; 344 }; 345 346 cooling-maps { 347 map0 { 348 trip = <&clus1_alarm>; 349 cooling-device = <&cpu2 4 4>, <&cpu3 4 4>; 350 }; 351 }; 352 }; 353 sys-thermal { 354 polling-delay-passive = <200>; /* ms */ 355 polling-delay = <1000>; /* ms */ 356 357 thermal-sensors = <&scmi_sensor 2>; 358 trips { 359 sys_alarm: sys-alarm { 360 temperature = <85000>; /* millicelsius */ 361 hysteresis = <1000>; /* millicelsius */ 362 type = "passive"; 363 }; 364 sys_shutdown: sys-shutdown { 365 temperature = <90000>; /* millicelsius */ 366 hysteresis = <0>; /* millicelsius */ 367 type = "critical"; 368 }; 369 }; 370 371 cooling-maps { 372 map0 { 373 trip = <&sys_alarm>; 374 cooling-device = <&cpu0 4 4>, 375 <&cpu1 4 4>, 376 <&cpu2 4 4>, 377 <&cpu3 4 4>; 378 }; 379 }; 380 }; 381 }; 382 383 iofpga_i2s: xlnx-i2s@1c150000 { 384 #sound-dai-cells = <0>; 385 compatible = "xlnx,i2s-transmitter-1.0"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 reg = <0x0 0x1c150000 0x0 0x10000>; 389 xlnx,dwidth = <0x18>; 390 xlnx,num-channels = <1>; 391 }; 392 393 audio_formatter: audio-formatter@1c100000 { 394 compatible = "xlnx,audio-formatter-1.0"; 395 reg = <0x0 0x1c000000 0x0 0x10000>; 396 #sound-dai-cells = <0>; 397 interrupt-names = "irq_mm2s"; 398 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 399 clock-names = "s_axi_lite_aclk", "aud_mclk", "m_axis_mm2s_aclk"; 400 clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>; 401 }; 402 403 sound { 404 compatible = "simple-audio-card"; 405 simple-audio-card,format = "i2s"; 406 simple-audio-card,bitclock-master = <&audio_master>; 407 simple-audio-card,frame-master = <&audio_master>; 408 audio_master: simple-audio-card,cpu { 409 sound-dai = <&iofpga_i2s>; 410 clocks = <&i2s_audclk>; 411 }; 412 413 simple-audio-card,codec { 414 sound-dai = <&hdmi_tx>; 415 }; 416 417 simple-audio-card,plat { 418 sound-dai = <&audio_formatter>; 419 }; 420 }; 421 422 i2s_audclk: i2s_audclk { 423 compatible = "fixed-clock"; 424 #clock-cells = <0>; 425 clock-frequency = <12288000>; 426 clock-output-names = "iofpga:i2s_audclk"; 427 }; 428}; 429 430&gic { 431 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 432 <0x0 0x300c0000 0 0x80000>; /* GICR */ 433 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 434 435 its1: msi-controller@30040000 { 436 compatible = "arm,gic-v3-its"; 437 msi-controller; 438 #msi-cells = <1>; 439 reg = <0x0 0x30040000 0x0 0x20000>; 440 }; 441 442 its2: msi-controller@30060000 { 443 compatible = "arm,gic-v3-its"; 444 msi-controller; 445 #msi-cells = <1>; 446 reg = <0x0 0x30060000 0x0 0x20000>; 447 }; 448 449 its_ccix: msi-controller@30080000 { 450 compatible = "arm,gic-v3-its"; 451 msi-controller; 452 #msi-cells = <1>; 453 reg = <0x0 0x30080000 0x0 0x20000>; 454 }; 455 456 its_pcie: msi-controller@300a0000 { 457 compatible = "arm,gic-v3-its"; 458 msi-controller; 459 #msi-cells = <1>; 460 reg = <0x0 0x300a0000 0x0 0x20000>; 461 }; 462}; 463