1/* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8#include "morello.dtsi" 9 10/ { 11 12 chosen { 13 stdout-path = "soc_uart0:115200n8"; 14 }; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 secure-firmware@ff000000 { 22 reg = <0 0xff000000 0 0x01000000>; 23 no-map; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 cpu0@0 { 31 compatible = "arm,armv8"; 32 reg = <0x0 0x0>; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 }; 36 cpu1@100 { 37 compatible = "arm,armv8"; 38 reg = <0x0 0x100>; 39 device_type = "cpu"; 40 enable-method = "psci"; 41 }; 42 cpu2@10000 { 43 compatible = "arm,armv8"; 44 reg = <0x0 0x10000>; 45 device_type = "cpu"; 46 enable-method = "psci"; 47 }; 48 cpu3@10100 { 49 compatible = "arm,armv8"; 50 reg = <0x0 0x10100>; 51 device_type = "cpu"; 52 enable-method = "psci"; 53 }; 54 }; 55 56 /* The first bank of memory, memory map is actually provided by UEFI. */ 57 memory@80000000 { 58 #address-cells = <2>; 59 #size-cells = <2>; 60 device_type = "memory"; 61 /* [0x80000000-0xffffffff] */ 62 reg = <0x00000000 0x80000000 0x0 0x7F000000>; 63 }; 64 65 memory@8080000000 { 66 #address-cells = <2>; 67 #size-cells = <2>; 68 device_type = "memory"; 69 /* [0x8080000000-0x83f7ffffff] */ 70 reg = <0x00000080 0x80000000 0x3 0x78000000>; 71 }; 72 73 smmu_pcie: iommu@4f400000 { 74 compatible = "arm,smmu-v3"; 75 reg = <0 0x4f400000 0 0x40000>; 76 interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, 77 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 78 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>, 79 <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>; 80 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 81 msi-parent = <&its2 0>; 82 #iommu-cells = <1>; 83 dma-coherent; 84 }; 85 86 pcie_ctlr: pcie@28c0000000 { 87 compatible = "pci-host-ecam-generic"; 88 device_type = "pci"; 89 reg = <0x28 0xC0000000 0 0x10000000>; 90 bus-range = <0 255>; 91 linux,pci-domain = <0>; 92 #address-cells = <3>; 93 #size-cells = <2>; 94 dma-coherent; 95 ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>, 96 <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>, 97 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>; 98 #interrupt-cells = <1>; 99 interrupt-map-mask = <0 0 0 7>; 100 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, 101 <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, 102 <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, 103 <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; 104 msi-map = <0 &its_pcie 0 0x10000>; 105 iommu-map = <0 &smmu_pcie 0 0x10000>; 106 status = "okay"; 107 }; 108 109 smmu_ccix: iommu@4f000000 { 110 compatible = "arm,smmu-v3"; 111 reg = <0 0x4f000000 0 0x40000>; 112 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 113 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 114 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 115 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; 116 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 117 msi-parent = <&its1 0>; 118 #iommu-cells = <1>; 119 dma-coherent; 120 }; 121 122 ccix_pcie_ctlr: pcie@4fc0000000 { 123 compatible = "pci-host-ecam-generic"; 124 device_type = "pci"; 125 reg = <0x4F 0xC0000000 0 0x10000000>; 126 bus-range = <0 255>; 127 linux,pci-domain = <1>; 128 #address-cells = <3>; 129 #size-cells = <2>; 130 dma-coherent; 131 ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>, 132 <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>, 133 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>; 134 #interrupt-cells = <1>; 135 interrupt-map-mask = <0 0 0 7>; 136 interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, 137 <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, 138 <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, 139 <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; 140 msi-map = <0 &its_ccix 0 0x10000>; 141 iommu-map = <0 &smmu_ccix 0 0x10000>; 142 status = "okay"; 143 }; 144 145 smmu_dp: iommu@2ce00000 { 146 compatible = "arm,smmu-v3"; 147 reg = <0 0x2ce00000 0 0x40000>; 148 interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 149 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 150 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>; 151 interrupt-names = "eventq", "cmdq-sync", "gerror"; 152 #iommu-cells = <1>; 153 }; 154 155 dp0: display@2cc00000 { 156 #address-cells = <1>; 157 #size-cells = <0>; 158 compatible = "arm,mali-d32"; 159 reg = <0 0x2cc00000 0 0x20000>; 160 interrupts = <0 69 4>; 161 interrupt-names = "DPU"; 162 clocks = <&dpu_aclk>; 163 clock-names = "aclk"; 164 iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, 165 <&smmu_dp 8>; 166 167 pl0: pipeline@0 { 168 reg = <0>; 169 clocks = <&dpu_pixel_clk>; 170 clock-names = "pxclk"; 171 pl_id = <0>; 172 ports { 173 #address-cells = <1>; 174 #size-cells = <0>; 175 port@0 { 176 reg = <0>; 177 dp_pl0_out0: endpoint { 178 remote-endpoint = <&tda998x_0_input>; 179 }; 180 }; 181 }; 182 }; 183 }; 184 185 i2c@1c0f0000 { 186 compatible = "cdns,i2c-r1p14"; 187 reg = <0x0 0x1c0f0000 0x0 0x1000>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 clock-frequency = <100000>; 191 i2c-sda-hold-time-ns = <500>; 192 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&dpu_aclk>; 194 195 hdmi-transmitter@70 { 196 compatible = "nxp,tda998x"; 197 reg = <0x70>; 198 video-ports = <0x234501>; 199 port { 200 tda998x_0_input: endpoint { 201 remote-endpoint = <&dp_pl0_out0>; 202 }; 203 }; 204 }; 205 }; 206 207 dpu_aclk: dpu_aclk { 208 /* 77.1 MHz derived from 24 MHz reference clock */ 209 compatible = "fixed-clock"; 210 #clock-cells = <0>; 211 clock-frequency = <350000000>; 212 clock-output-names = "aclk"; 213 }; 214 215 dpu_pixel_clk: dpu-pixel-clk { 216 compatible = "fixed-clock"; 217 #clock-cells = <0>; 218 clock-frequency = <148500000>; 219 clock-output-names = "pxclk"; 220 }; 221}; 222 223&gic { 224 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 225 <0x0 0x300c0000 0 0x80000>; /* GICR */ 226 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 227 228 its1: its@30040000 { 229 compatible = "arm,gic-v3-its"; 230 msi-controller; 231 #msi-cells = <1>; 232 reg = <0x0 0x30040000 0x0 0x20000>; 233 }; 234 235 its2: its@30060000 { 236 compatible = "arm,gic-v3-its"; 237 msi-controller; 238 #msi-cells = <1>; 239 reg = <0x0 0x30060000 0x0 0x20000>; 240 }; 241 242 its_ccix: its@30080000 { 243 compatible = "arm,gic-v3-its"; 244 msi-controller; 245 #msi-cells = <1>; 246 reg = <0x0 0x30080000 0x0 0x20000>; 247 }; 248 249 its_pcie: its@300a0000 { 250 compatible = "arm,gic-v3-its"; 251 msi-controller; 252 #msi-cells = <1>; 253 reg = <0x0 0x300a0000 0x0 0x20000>; 254 }; 255}; 256