1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31/dts-v1/; 32 33/memreserve/ 0x80000000 0x00010000; 34 35/ { 36}; 37 38/ { 39 model = "FVP Base"; 40 compatible = "arm,vfp-base", "arm,vexpress"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 chosen { }; 46 47 aliases { 48 serial0 = &v2m_serial0; 49 serial1 = &v2m_serial1; 50 serial2 = &v2m_serial2; 51 serial3 = &v2m_serial3; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 56 method = "smc"; 57 cpu_suspend = <0xc4000001>; 58 cpu_off = <0x84000002>; 59 cpu_on = <0xc4000003>; 60 sys_poweroff = <0x84000008>; 61 sys_reset = <0x84000009>; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 }; 83 84 cluster1 { 85 core0 { 86 cpu = <&CPU4>; 87 }; 88 core1 { 89 cpu = <&CPU5>; 90 }; 91 core2 { 92 cpu = <&CPU6>; 93 }; 94 core3 { 95 cpu = <&CPU7>; 96 }; 97 }; 98 }; 99 100 idle-states { 101 entry-method = "arm,psci"; 102 103 CPU_SLEEP_0: cpu-sleep-0 { 104 compatible = "arm,idle-state"; 105 local-timer-stop; 106 arm,psci-suspend-param = <0x0010000>; 107 entry-latency-us = <40>; 108 exit-latency-us = <100>; 109 min-residency-us = <150>; 110 }; 111 112 CLUSTER_SLEEP_0: cluster-sleep-0 { 113 compatible = "arm,idle-state"; 114 local-timer-stop; 115 arm,psci-suspend-param = <0x1010000>; 116 entry-latency-us = <500>; 117 exit-latency-us = <1000>; 118 min-residency-us = <2500>; 119 }; 120 }; 121 122 CPU0:cpu@0 { 123 device_type = "cpu"; 124 compatible = "arm,armv8"; 125 reg = <0x0 0x0>; 126 enable-method = "psci"; 127 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 128 next-level-cache = <&L2_0>; 129 }; 130 131 CPU1:cpu@1 { 132 device_type = "cpu"; 133 compatible = "arm,armv8"; 134 reg = <0x0 0x1>; 135 enable-method = "psci"; 136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 137 next-level-cache = <&L2_0>; 138 }; 139 140 CPU2:cpu@2 { 141 device_type = "cpu"; 142 compatible = "arm,armv8"; 143 reg = <0x0 0x2>; 144 enable-method = "psci"; 145 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 146 next-level-cache = <&L2_0>; 147 }; 148 149 CPU3:cpu@3 { 150 device_type = "cpu"; 151 compatible = "arm,armv8"; 152 reg = <0x0 0x3>; 153 enable-method = "psci"; 154 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 155 next-level-cache = <&L2_0>; 156 }; 157 158 CPU4:cpu@100 { 159 device_type = "cpu"; 160 compatible = "arm,armv8"; 161 reg = <0x0 0x100>; 162 enable-method = "psci"; 163 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 164 next-level-cache = <&L2_0>; 165 }; 166 167 CPU5:cpu@101 { 168 device_type = "cpu"; 169 compatible = "arm,armv8"; 170 reg = <0x0 0x101>; 171 enable-method = "psci"; 172 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 173 next-level-cache = <&L2_0>; 174 }; 175 176 CPU6:cpu@102 { 177 device_type = "cpu"; 178 compatible = "arm,armv8"; 179 reg = <0x0 0x102>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 182 next-level-cache = <&L2_0>; 183 }; 184 185 CPU7:cpu@103 { 186 device_type = "cpu"; 187 compatible = "arm,armv8"; 188 reg = <0x0 0x103>; 189 enable-method = "psci"; 190 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 191 next-level-cache = <&L2_0>; 192 }; 193 194 L2_0: l2-cache0 { 195 compatible = "cache"; 196 }; 197 }; 198 199 memory@80000000 { 200 device_type = "memory"; 201 reg = <0x00000000 0x80000000 0 0x7F000000>, 202 <0x00000008 0x80000000 0 0x80000000>; 203 }; 204 205 gic: interrupt-controller@2f000000 { 206 compatible = "arm,gic-v3"; 207 #interrupt-cells = <3>; 208 #address-cells = <2>; 209 #size-cells = <2>; 210 ranges; 211 interrupt-controller; 212 reg = <0x0 0x2f000000 0 0x10000>, // GICD 213 <0x0 0x2f100000 0 0x200000>, // GICR 214 <0x0 0x2c000000 0 0x2000>, // GICC 215 <0x0 0x2c010000 0 0x2000>, // GICH 216 <0x0 0x2c02f000 0 0x2000>; // GICV 217 interrupts = <1 9 4>; 218 219 its: its@2f020000 { 220 compatible = "arm,gic-v3-its"; 221 msi-controller; 222 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS 223 }; 224 }; 225 226 timer { 227 compatible = "arm,armv8-timer"; 228 interrupts = <1 13 0xff01>, 229 <1 14 0xff01>, 230 <1 11 0xff01>, 231 <1 10 0xff01>; 232 clock-frequency = <100000000>; 233 }; 234 235 timer@2a810000 { 236 compatible = "arm,armv7-timer-mem"; 237 reg = <0x0 0x2a810000 0x0 0x10000>; 238 clock-frequency = <100000000>; 239 #address-cells = <2>; 240 #size-cells = <2>; 241 ranges; 242 frame@2a830000 { 243 frame-number = <1>; 244 interrupts = <0 26 4>; 245 reg = <0x0 0x2a830000 0x0 0x10000>; 246 }; 247 }; 248 249 pmu { 250 compatible = "arm,armv8-pmuv3"; 251 interrupts = <0 60 4>, 252 <0 61 4>, 253 <0 62 4>, 254 <0 63 4>; 255 }; 256 257 smb { 258 compatible = "simple-bus"; 259 260 #address-cells = <2>; 261 #size-cells = <1>; 262 ranges = <0 0 0 0x08000000 0x04000000>, 263 <1 0 0 0x14000000 0x04000000>, 264 <2 0 0 0x18000000 0x04000000>, 265 <3 0 0 0x1c000000 0x04000000>, 266 <4 0 0 0x0c000000 0x04000000>, 267 <5 0 0 0x10000000 0x04000000>; 268 269 #interrupt-cells = <1>; 270 interrupt-map-mask = <0 0 63>; 271 interrupt-map = <0 0 0 &gic 0 0 0 0 4>, 272 <0 0 1 &gic 0 0 0 1 4>, 273 <0 0 2 &gic 0 0 0 2 4>, 274 <0 0 3 &gic 0 0 0 3 4>, 275 <0 0 4 &gic 0 0 0 4 4>, 276 <0 0 5 &gic 0 0 0 5 4>, 277 <0 0 6 &gic 0 0 0 6 4>, 278 <0 0 7 &gic 0 0 0 7 4>, 279 <0 0 8 &gic 0 0 0 8 4>, 280 <0 0 9 &gic 0 0 0 9 4>, 281 <0 0 10 &gic 0 0 0 10 4>, 282 <0 0 11 &gic 0 0 0 11 4>, 283 <0 0 12 &gic 0 0 0 12 4>, 284 <0 0 13 &gic 0 0 0 13 4>, 285 <0 0 14 &gic 0 0 0 14 4>, 286 <0 0 15 &gic 0 0 0 15 4>, 287 <0 0 16 &gic 0 0 0 16 4>, 288 <0 0 17 &gic 0 0 0 17 4>, 289 <0 0 18 &gic 0 0 0 18 4>, 290 <0 0 19 &gic 0 0 0 19 4>, 291 <0 0 20 &gic 0 0 0 20 4>, 292 <0 0 21 &gic 0 0 0 21 4>, 293 <0 0 22 &gic 0 0 0 22 4>, 294 <0 0 23 &gic 0 0 0 23 4>, 295 <0 0 24 &gic 0 0 0 24 4>, 296 <0 0 25 &gic 0 0 0 25 4>, 297 <0 0 26 &gic 0 0 0 26 4>, 298 <0 0 27 &gic 0 0 0 27 4>, 299 <0 0 28 &gic 0 0 0 28 4>, 300 <0 0 29 &gic 0 0 0 29 4>, 301 <0 0 30 &gic 0 0 0 30 4>, 302 <0 0 31 &gic 0 0 0 31 4>, 303 <0 0 32 &gic 0 0 0 32 4>, 304 <0 0 33 &gic 0 0 0 33 4>, 305 <0 0 34 &gic 0 0 0 34 4>, 306 <0 0 35 &gic 0 0 0 35 4>, 307 <0 0 36 &gic 0 0 0 36 4>, 308 <0 0 37 &gic 0 0 0 37 4>, 309 <0 0 38 &gic 0 0 0 38 4>, 310 <0 0 39 &gic 0 0 0 39 4>, 311 <0 0 40 &gic 0 0 0 40 4>, 312 <0 0 41 &gic 0 0 0 41 4>, 313 <0 0 42 &gic 0 0 0 42 4>; 314 315 /include/ "rtsm_ve-motherboard.dtsi" 316 }; 317 318 panels { 319 panel@0 { 320 compatible = "panel"; 321 mode = "XVGA"; 322 refresh = <60>; 323 xres = <1024>; 324 yres = <768>; 325 pixclock = <15748>; 326 left_margin = <152>; 327 right_margin = <48>; 328 upper_margin = <23>; 329 lower_margin = <3>; 330 hsync_len = <104>; 331 vsync_len = <4>; 332 sync = <0>; 333 vmode = "FB_VMODE_NONINTERLACED"; 334 tim2 = "TIM2_BCD", "TIM2_IPC"; 335 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; 336 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; 337 bpp = <16>; 338 }; 339 }; 340}; 341