1/* 2 * Copyright (c) 2019, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9/ { 10 model = "A5DS"; 11 compatible = "arm,A5DS"; 12 interrupt-parent = <&gic>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 psci { 17 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 18 method = "smc"; 19 cpu_on = <0x84000003>; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 enable-method = "psci"; 26 cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a5"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 }; 32 cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a5"; 35 reg = <1>; 36 next-level-cache = <&L2>; 37 }; 38 cpu@2 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a5"; 41 reg = <2>; 42 next-level-cache = <&L2>; 43 }; 44 cpu@3 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a5"; 47 reg = <3>; 48 next-level-cache = <&L2>; 49 }; 50 }; 51 52 memory@80000000 { 53 device_type = "memory"; 54 reg = <0x80000000 0x7F000000>; 55 }; 56 57 L2: cache-controller@1C010000 { 58 compatible = "arm,pl310-cache"; 59 reg = <0x1C010000 0x1000>; 60 interrupts = <0 84 4>; 61 cache-level = <2>; 62 cache-unified; 63 arm,data-latency = <1 1 1>; 64 arm,tag-latency = <1 1 1>; 65 }; 66 67 refclk100mhz: refclk100mhz { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <100000000>; 71 clock-output-names = "apb_pclk"; 72 }; 73 74 smbclk: refclk24mhzx2 { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <48000000>; 78 clock-output-names = "smclk"; 79 }; 80 81 82 rtc@1a220000 { 83 compatible = "arm,pl031", "arm,primecell"; 84 reg = <0x1a220000 0x1000>; 85 clocks = <&refclk100mhz>; 86 interrupts = <0 6 0xf04>; 87 clock-names = "apb_pclk"; 88 }; 89 90 gic: interrupt-controller@1c001000 { 91 compatible = "arm,cortex-a9-gic"; 92 #interrupt-cells = <3>; 93 #address-cells = <0>; 94 interrupt-controller; 95 reg = <0x1c001000 0x1000>, 96 <0x1c000100 0x100>; 97 interrupts = <1 9 0xf04>; 98 }; 99 100 serial0: uart@1a200000 { 101 compatible = "arm,pl011", "arm,primecell"; 102 reg = <0x1a200000 0x1000>; 103 interrupt-parent = <&gic>; 104 interrupts = <0 8 0xf04>; 105 clocks = <&refclk100mhz>; 106 clock-names = "apb_pclk"; 107 }; 108 109 serial1: uart@1a210000 { 110 compatible = "arm,pl011", "arm,primecell"; 111 reg = <0x1a210000 0x1000>; 112 interrupt-parent = <&gic>; 113 interrupts = <0 9 0xf04>; 114 clocks = <&refclk100mhz>; 115 clock-names = "apb_pclk"; 116 }; 117 118 timer0: timer@1a040000 { 119 compatible = "arm,armv7-timer-mem"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges; 123 reg = <0x1a040000 0x1000>; 124 clock-frequency = <50000000>; 125 126 frame@1a050000 { 127 frame-number = <0>; 128 interrupts = <0 2 0xf04>; 129 reg = <0x1a050000 0x1000>; 130 }; 131 }; 132}; 133