1*00c7d5acSUsama Arif/* 2*00c7d5acSUsama Arif * Copyright (c) 2019, Arm Limited. All rights reserved. 3*00c7d5acSUsama Arif * 4*00c7d5acSUsama Arif * SPDX-License-Identifier: BSD-3-Clause 5*00c7d5acSUsama Arif */ 6*00c7d5acSUsama Arif 7*00c7d5acSUsama Arif/dts-v1/; 8*00c7d5acSUsama Arif 9*00c7d5acSUsama Arif/ { 10*00c7d5acSUsama Arif model = "A5DS"; 11*00c7d5acSUsama Arif compatible = "arm,A5DS"; 12*00c7d5acSUsama Arif interrupt-parent = <&gic>; 13*00c7d5acSUsama Arif #address-cells = <1>; 14*00c7d5acSUsama Arif #size-cells = <1>; 15*00c7d5acSUsama Arif cpus { 16*00c7d5acSUsama Arif #address-cells = <1>; 17*00c7d5acSUsama Arif #size-cells = <0>; 18*00c7d5acSUsama Arif cpu@0 { 19*00c7d5acSUsama Arif device_type = "cpu"; 20*00c7d5acSUsama Arif compatible = "arm,cortex-a5"; 21*00c7d5acSUsama Arif reg = <0>; 22*00c7d5acSUsama Arif }; 23*00c7d5acSUsama Arif }; 24*00c7d5acSUsama Arif 25*00c7d5acSUsama Arif memory@80000000 { 26*00c7d5acSUsama Arif device_type = "memory"; 27*00c7d5acSUsama Arif reg = <0x80000000 0x7F000000>; 28*00c7d5acSUsama Arif }; 29*00c7d5acSUsama Arif 30*00c7d5acSUsama Arif refclk100mhz: refclk100mhz { 31*00c7d5acSUsama Arif compatible = "fixed-clock"; 32*00c7d5acSUsama Arif #clock-cells = <0>; 33*00c7d5acSUsama Arif clock-frequency = <100000000>; 34*00c7d5acSUsama Arif clock-output-names = "apb_pclk"; 35*00c7d5acSUsama Arif }; 36*00c7d5acSUsama Arif 37*00c7d5acSUsama Arif smbclk: refclk24mhzx2 { 38*00c7d5acSUsama Arif compatible = "fixed-clock"; 39*00c7d5acSUsama Arif #clock-cells = <0>; 40*00c7d5acSUsama Arif clock-frequency = <48000000>; 41*00c7d5acSUsama Arif clock-output-names = "smclk"; 42*00c7d5acSUsama Arif }; 43*00c7d5acSUsama Arif 44*00c7d5acSUsama Arif 45*00c7d5acSUsama Arif rtc@1a220000 { 46*00c7d5acSUsama Arif compatible = "arm,pl031", "arm,primecell"; 47*00c7d5acSUsama Arif reg = <0x1a220000 0x1000>; 48*00c7d5acSUsama Arif clocks = <&refclk100mhz>; 49*00c7d5acSUsama Arif interrupts = <0 6 0xf04>; 50*00c7d5acSUsama Arif clock-names = "apb_pclk"; 51*00c7d5acSUsama Arif }; 52*00c7d5acSUsama Arif 53*00c7d5acSUsama Arif gic: interrupt-controller@1c001000 { 54*00c7d5acSUsama Arif compatible = "arm,cortex-a9-gic"; 55*00c7d5acSUsama Arif #interrupt-cells = <3>; 56*00c7d5acSUsama Arif #address-cells = <0>; 57*00c7d5acSUsama Arif interrupt-controller; 58*00c7d5acSUsama Arif reg = <0x1c001000 0x1000>, 59*00c7d5acSUsama Arif <0x1c000100 0x100>; 60*00c7d5acSUsama Arif interrupts = <1 9 0xf04>; 61*00c7d5acSUsama Arif }; 62*00c7d5acSUsama Arif 63*00c7d5acSUsama Arif serial0: uart@1a200000 { 64*00c7d5acSUsama Arif compatible = "arm,pl011", "arm,primecell"; 65*00c7d5acSUsama Arif reg = <0x1a200000 0x1000>; 66*00c7d5acSUsama Arif interrupt-parent = <&gic>; 67*00c7d5acSUsama Arif interrupts = <0 8 0xf04>; 68*00c7d5acSUsama Arif clocks = <&refclk100mhz>; 69*00c7d5acSUsama Arif clock-names = "apb_pclk"; 70*00c7d5acSUsama Arif }; 71*00c7d5acSUsama Arif 72*00c7d5acSUsama Arif serial1: uart@1a210000 { 73*00c7d5acSUsama Arif compatible = "arm,pl011", "arm,primecell"; 74*00c7d5acSUsama Arif reg = <0x1a210000 0x1000>; 75*00c7d5acSUsama Arif interrupt-parent = <&gic>; 76*00c7d5acSUsama Arif interrupts = <0 9 0xf04>; 77*00c7d5acSUsama Arif clocks = <&refclk100mhz>; 78*00c7d5acSUsama Arif clock-names = "apb_pclk"; 79*00c7d5acSUsama Arif }; 80*00c7d5acSUsama Arif 81*00c7d5acSUsama Arif timer0: timer@1a040000 { 82*00c7d5acSUsama Arif compatible = "arm,armv7-timer-mem"; 83*00c7d5acSUsama Arif #address-cells = <1>; 84*00c7d5acSUsama Arif #size-cells = <1>; 85*00c7d5acSUsama Arif ranges; 86*00c7d5acSUsama Arif reg = <0x1a040000 0x1000>; 87*00c7d5acSUsama Arif clock-frequency = <50000000>; 88*00c7d5acSUsama Arif 89*00c7d5acSUsama Arif frame@1a050000 { 90*00c7d5acSUsama Arif frame-number = <0>; 91*00c7d5acSUsama Arif interrupts = <0 2 0xf04>; 92*00c7d5acSUsama Arif reg = <0x1a050000 0x1000>; 93*00c7d5acSUsama Arif }; 94*00c7d5acSUsama Arif }; 95*00c7d5acSUsama Arif}; 96