1 /* 2 * Copyright (c) 2025-2026 Texas Instruments Incorporated - https://www.ti.com 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * TI 16FFT PLL API Header 9 * 10 * This header defines the 16FFT (16-bit Fractional Feedback) PLL specific 11 * data structures and driver interface. It provides the register layouts, 12 * HSDIV configuration, and driver operations for TI's fractional-N PLL 13 * variant supporting VCO frequencies from 800 MHz to 3.2 GHz. 14 */ 15 16 #ifndef TI_CLK_PLL_16FFT_H 17 #define TI_CLK_PLL_16FFT_H 18 19 #include <ti_clk_pll.h> 20 21 /* 22 * 16FFT PLL clock driver data 23 * 24 * Extends the base PLL data structure with 16FFT-specific register base 25 * address and HSDIV output index. Used by the 16FFT PLL driver to manage 26 * fractional-N PLL instances and their high-speed divider outputs. 27 */ 28 struct ti_clk_data_pll_16fft { 29 /* Base PLL driver data (frequency, dividers, etc.) */ 30 struct ti_clk_data_pll data_pll; 31 /* Physical base address of the PLL register block */ 32 uint32_t base; 33 /* HSDIV output index (0-15) for this clock instance */ 34 uint8_t idx; 35 }; 36 37 /* 38 * Main 16FFT PLL clock driver 39 * 40 * Provides clock operations for the 16FFT PLL core including initialization, 41 * frequency query, VCO configuration, and lock management. 42 */ 43 extern const struct ti_clk_drv ti_clk_drv_pll_16fft; 44 45 /* 46 * 16FFT PLL post-divider driver 47 * 48 * Manages the programmable post-divider stage that divides the VCO output 49 * before distribution. Supports divide ratios from 1 to 16. 50 */ 51 extern const struct ti_clk_drv_div ti_clk_drv_div_pll_16fft_postdiv; 52 53 /* 54 * 16FFT PLL HSDIV output driver 55 * 56 * Controls individual high-speed divider outputs (HSDIV0-HSDIV15) that 57 * divide the post-divided PLL output. Each HSDIV supports independent 58 * divide ratios from 1 to 128. 59 */ 60 extern const struct ti_clk_drv_div ti_clk_drv_div_pll_16fft_hsdiv; 61 62 /* 63 * 16FFT PLL combined post-divider and HSDIV driver 64 * 65 * Composite driver managing both the post-divider and HSDIV stages as a 66 * single clock node. Used for clocks that control the complete divider chain 67 * from VCO to final output. 68 */ 69 extern const struct ti_clk_drv_div ti_clk_drv_div_pll_16fft_postdiv_hsdiv; 70 71 #endif /* TI_CLK_PLL_16FFT_H */ 72