1 /* 2 * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <libfdt.h> 8 9 #include <platform_def.h> 10 11 #include <common/debug.h> 12 #include <common/fdt_wrappers.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/spi_mem.h> 15 #include <drivers/st/stm32_gpio.h> 16 #include <drivers/st/stm32_qspi.h> 17 #include <drivers/st/stm32mp_reset.h> 18 #include <lib/mmio.h> 19 #include <lib/utils_def.h> 20 21 /* Timeout for device interface reset */ 22 #define TIMEOUT_US_1_MS 1000U 23 24 /* QUADSPI registers */ 25 #define QSPI_CR 0x00U 26 #define QSPI_DCR 0x04U 27 #define QSPI_SR 0x08U 28 #define QSPI_FCR 0x0CU 29 #define QSPI_DLR 0x10U 30 #define QSPI_CCR 0x14U 31 #define QSPI_AR 0x18U 32 #define QSPI_ABR 0x1CU 33 #define QSPI_DR 0x20U 34 #define QSPI_PSMKR 0x24U 35 #define QSPI_PSMAR 0x28U 36 #define QSPI_PIR 0x2CU 37 #define QSPI_LPTR 0x30U 38 39 /* QUADSPI control register */ 40 #define QSPI_CR_EN BIT(0) 41 #define QSPI_CR_ABORT BIT(1) 42 #define QSPI_CR_DMAEN BIT(2) 43 #define QSPI_CR_TCEN BIT(3) 44 #define QSPI_CR_SSHIFT BIT(4) 45 #define QSPI_CR_DFM BIT(6) 46 #define QSPI_CR_FSEL BIT(7) 47 #define QSPI_CR_FTHRES_SHIFT 8U 48 #define QSPI_CR_TEIE BIT(16) 49 #define QSPI_CR_TCIE BIT(17) 50 #define QSPI_CR_FTIE BIT(18) 51 #define QSPI_CR_SMIE BIT(19) 52 #define QSPI_CR_TOIE BIT(20) 53 #define QSPI_CR_APMS BIT(22) 54 #define QSPI_CR_PMM BIT(23) 55 #define QSPI_CR_PRESCALER_MASK GENMASK_32(31, 24) 56 #define QSPI_CR_PRESCALER_SHIFT 24U 57 58 /* QUADSPI device configuration register */ 59 #define QSPI_DCR_CKMODE BIT(0) 60 #define QSPI_DCR_CSHT_MASK GENMASK_32(10, 8) 61 #define QSPI_DCR_CSHT_SHIFT 8U 62 #define QSPI_DCR_FSIZE_MASK GENMASK_32(20, 16) 63 #define QSPI_DCR_FSIZE_SHIFT 16U 64 65 /* QUADSPI status register */ 66 #define QSPI_SR_TEF BIT(0) 67 #define QSPI_SR_TCF BIT(1) 68 #define QSPI_SR_FTF BIT(2) 69 #define QSPI_SR_SMF BIT(3) 70 #define QSPI_SR_TOF BIT(4) 71 #define QSPI_SR_BUSY BIT(5) 72 73 /* QUADSPI flag clear register */ 74 #define QSPI_FCR_CTEF BIT(0) 75 #define QSPI_FCR_CTCF BIT(1) 76 #define QSPI_FCR_CSMF BIT(3) 77 #define QSPI_FCR_CTOF BIT(4) 78 79 /* QUADSPI communication configuration register */ 80 #define QSPI_CCR_DDRM BIT(31) 81 #define QSPI_CCR_DHHC BIT(30) 82 #define QSPI_CCR_SIOO BIT(28) 83 #define QSPI_CCR_FMODE_SHIFT 26U 84 #define QSPI_CCR_DMODE_SHIFT 24U 85 #define QSPI_CCR_DCYC_SHIFT 18U 86 #define QSPI_CCR_ABSIZE_SHIFT 16U 87 #define QSPI_CCR_ABMODE_SHIFT 14U 88 #define QSPI_CCR_ADSIZE_SHIFT 12U 89 #define QSPI_CCR_ADMODE_SHIFT 10U 90 #define QSPI_CCR_IMODE_SHIFT 8U 91 #define QSPI_CCR_IND_WRITE 0U 92 #define QSPI_CCR_IND_READ 1U 93 #define QSPI_CCR_MEM_MAP 3U 94 95 #define QSPI_MAX_CHIP 2U 96 97 #define QSPI_FIFO_TIMEOUT_US 30U 98 #define QSPI_CMD_TIMEOUT_US 1000U 99 #define QSPI_BUSY_TIMEOUT_US 100U 100 #define QSPI_ABT_TIMEOUT_US 100U 101 102 #define DT_QSPI_COMPAT "st,stm32f469-qspi" 103 104 #define FREQ_100MHZ 100000000U 105 106 struct stm32_qspi_ctrl { 107 uintptr_t reg_base; 108 uintptr_t mm_base; 109 size_t mm_size; 110 unsigned long clock_id; 111 unsigned int reset_id; 112 }; 113 114 static struct stm32_qspi_ctrl stm32_qspi; 115 116 static uintptr_t qspi_base(void) 117 { 118 return stm32_qspi.reg_base; 119 } 120 121 static int stm32_qspi_wait_for_not_busy(void) 122 { 123 uint64_t timeout = timeout_init_us(QSPI_BUSY_TIMEOUT_US); 124 125 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) { 126 if (timeout_elapsed(timeout)) { 127 ERROR("%s: busy timeout\n", __func__); 128 return -ETIMEDOUT; 129 } 130 } 131 132 return 0; 133 } 134 135 static int stm32_qspi_wait_cmd(const struct spi_mem_op *op) 136 { 137 int ret = 0; 138 uint64_t timeout; 139 140 if (op->data.nbytes == 0U) { 141 return stm32_qspi_wait_for_not_busy(); 142 } 143 144 timeout = timeout_init_us(QSPI_CMD_TIMEOUT_US); 145 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) { 146 if (timeout_elapsed(timeout)) { 147 ret = -ETIMEDOUT; 148 break; 149 } 150 } 151 152 if (ret == 0) { 153 if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) { 154 ERROR("%s: transfer error\n", __func__); 155 ret = -EIO; 156 } 157 } else { 158 ERROR("%s: cmd timeout\n", __func__); 159 } 160 161 /* Clear flags */ 162 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF); 163 164 return ret; 165 } 166 167 static void stm32_qspi_read_fifo(uint8_t *val, uintptr_t addr) 168 { 169 *val = mmio_read_8(addr); 170 } 171 172 static void stm32_qspi_write_fifo(uint8_t *val, uintptr_t addr) 173 { 174 mmio_write_8(addr, *val); 175 } 176 177 static int stm32_qspi_poll(const struct spi_mem_op *op) 178 { 179 void (*fifo)(uint8_t *val, uintptr_t addr); 180 uint32_t len; 181 uint8_t *buf; 182 183 if (op->data.dir == SPI_MEM_DATA_IN) { 184 fifo = stm32_qspi_read_fifo; 185 } else { 186 fifo = stm32_qspi_write_fifo; 187 } 188 189 buf = (uint8_t *)op->data.buf; 190 191 for (len = op->data.nbytes; len != 0U; len--) { 192 uint64_t timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US); 193 194 while ((mmio_read_32(qspi_base() + QSPI_SR) & 195 QSPI_SR_FTF) == 0U) { 196 if (timeout_elapsed(timeout)) { 197 ERROR("%s: fifo timeout\n", __func__); 198 return -ETIMEDOUT; 199 } 200 } 201 202 fifo(buf++, qspi_base() + QSPI_DR); 203 } 204 205 return 0; 206 } 207 208 static int stm32_qspi_mm(const struct spi_mem_op *op) 209 { 210 memcpy(op->data.buf, 211 (void *)(stm32_qspi.mm_base + (size_t)op->addr.val), 212 op->data.nbytes); 213 214 return 0; 215 } 216 217 static int stm32_qspi_tx(const struct spi_mem_op *op, uint8_t mode) 218 { 219 if (op->data.nbytes == 0U) { 220 return 0; 221 } 222 223 if (mode == QSPI_CCR_MEM_MAP) { 224 return stm32_qspi_mm(op); 225 } 226 227 return stm32_qspi_poll(op); 228 } 229 230 static unsigned int stm32_qspi_get_mode(uint8_t buswidth) 231 { 232 if (buswidth == 4U) { 233 return 3U; 234 } 235 236 return buswidth; 237 } 238 239 static int stm32_qspi_exec_op(const struct spi_mem_op *op) 240 { 241 uint64_t timeout; 242 uint32_t ccr; 243 size_t addr_max; 244 uint8_t mode = QSPI_CCR_IND_WRITE; 245 int ret; 246 247 VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addr:%llx len:%x\n", 248 __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 249 op->dummy.buswidth, op->data.buswidth, 250 op->addr.val, op->data.nbytes); 251 252 ret = stm32_qspi_wait_for_not_busy(); 253 if (ret != 0) { 254 return ret; 255 } 256 257 addr_max = op->addr.val + op->data.nbytes + 1U; 258 259 if ((op->data.dir == SPI_MEM_DATA_IN) && (op->data.nbytes != 0U)) { 260 if ((addr_max < stm32_qspi.mm_size) && 261 (op->addr.buswidth != 0U)) { 262 mode = QSPI_CCR_MEM_MAP; 263 } else { 264 mode = QSPI_CCR_IND_READ; 265 } 266 } 267 268 if (op->data.nbytes != 0U) { 269 mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U); 270 } 271 272 ccr = mode << QSPI_CCR_FMODE_SHIFT; 273 ccr |= op->cmd.opcode; 274 ccr |= stm32_qspi_get_mode(op->cmd.buswidth) << QSPI_CCR_IMODE_SHIFT; 275 276 if (op->addr.nbytes != 0U) { 277 ccr |= (op->addr.nbytes - 1U) << QSPI_CCR_ADSIZE_SHIFT; 278 ccr |= stm32_qspi_get_mode(op->addr.buswidth) << 279 QSPI_CCR_ADMODE_SHIFT; 280 } 281 282 if ((op->dummy.buswidth != 0U) && (op->dummy.nbytes != 0U)) { 283 ccr |= (op->dummy.nbytes * 8U / op->dummy.buswidth) << 284 QSPI_CCR_DCYC_SHIFT; 285 } 286 287 if (op->data.nbytes != 0U) { 288 ccr |= stm32_qspi_get_mode(op->data.buswidth) << 289 QSPI_CCR_DMODE_SHIFT; 290 } 291 292 mmio_write_32(qspi_base() + QSPI_CCR, ccr); 293 294 if ((op->addr.nbytes != 0U) && (mode != QSPI_CCR_MEM_MAP)) { 295 mmio_write_32(qspi_base() + QSPI_AR, op->addr.val); 296 } 297 298 ret = stm32_qspi_tx(op, mode); 299 300 /* 301 * Abort in: 302 * - Error case. 303 * - Memory mapped read: prefetching must be stopped if we read the last 304 * byte of device (device size - fifo size). If device size is not 305 * known then prefetching is always stopped. 306 */ 307 if ((ret != 0) || (mode == QSPI_CCR_MEM_MAP)) { 308 goto abort; 309 } 310 311 /* Wait end of TX in indirect mode */ 312 ret = stm32_qspi_wait_cmd(op); 313 if (ret != 0) { 314 goto abort; 315 } 316 317 return 0; 318 319 abort: 320 mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT); 321 322 /* Wait clear of abort bit by hardware */ 323 timeout = timeout_init_us(QSPI_ABT_TIMEOUT_US); 324 while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) { 325 if (timeout_elapsed(timeout)) { 326 ret = -ETIMEDOUT; 327 break; 328 } 329 } 330 331 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF); 332 333 if (ret != 0) { 334 ERROR("%s: exec op error\n", __func__); 335 } 336 337 return ret; 338 } 339 340 static int stm32_qspi_claim_bus(unsigned int cs) 341 { 342 uint32_t cr; 343 344 if (cs >= QSPI_MAX_CHIP) { 345 return -ENODEV; 346 } 347 348 /* Set chip select and enable the controller */ 349 cr = QSPI_CR_EN; 350 if (cs == 1U) { 351 cr |= QSPI_CR_FSEL; 352 } 353 354 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr); 355 356 return 0; 357 } 358 359 static void stm32_qspi_release_bus(void) 360 { 361 mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN); 362 } 363 364 static int stm32_qspi_set_speed(unsigned int hz) 365 { 366 unsigned long qspi_clk = stm32mp_clk_get_rate(stm32_qspi.clock_id); 367 uint32_t prescaler = UINT8_MAX; 368 uint32_t csht; 369 int ret; 370 371 if (qspi_clk == 0U) { 372 return -EINVAL; 373 } 374 375 if (hz > 0U) { 376 prescaler = div_round_up(qspi_clk, hz) - 1U; 377 if (prescaler > UINT8_MAX) { 378 prescaler = UINT8_MAX; 379 } 380 } 381 382 csht = div_round_up((5U * qspi_clk) / (prescaler + 1U), FREQ_100MHZ); 383 csht = ((csht - 1U) << QSPI_DCR_CSHT_SHIFT) & QSPI_DCR_CSHT_MASK; 384 385 ret = stm32_qspi_wait_for_not_busy(); 386 if (ret != 0) { 387 return ret; 388 } 389 390 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK, 391 prescaler << QSPI_CR_PRESCALER_SHIFT); 392 393 mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht); 394 395 VERBOSE("%s: speed=%lu\n", __func__, qspi_clk / (prescaler + 1U)); 396 397 return 0; 398 } 399 400 static int stm32_qspi_set_mode(unsigned int mode) 401 { 402 int ret; 403 404 ret = stm32_qspi_wait_for_not_busy(); 405 if (ret != 0) { 406 return ret; 407 } 408 409 if ((mode & SPI_CS_HIGH) != 0U) { 410 return -ENODEV; 411 } 412 413 if (((mode & SPI_CPHA) != 0U) && ((mode & SPI_CPOL) != 0U)) { 414 mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); 415 } else if (((mode & SPI_CPHA) == 0U) && ((mode & SPI_CPOL) == 0U)) { 416 mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); 417 } else { 418 return -ENODEV; 419 } 420 421 VERBOSE("%s: mode=0x%x\n", __func__, mode); 422 423 if ((mode & SPI_RX_QUAD) != 0U) { 424 VERBOSE("rx: quad\n"); 425 } else if ((mode & SPI_RX_DUAL) != 0U) { 426 VERBOSE("rx: dual\n"); 427 } else { 428 VERBOSE("rx: single\n"); 429 } 430 431 if ((mode & SPI_TX_QUAD) != 0U) { 432 VERBOSE("tx: quad\n"); 433 } else if ((mode & SPI_TX_DUAL) != 0U) { 434 VERBOSE("tx: dual\n"); 435 } else { 436 VERBOSE("tx: single\n"); 437 } 438 439 return 0; 440 } 441 442 static const struct spi_bus_ops stm32_qspi_bus_ops = { 443 .claim_bus = stm32_qspi_claim_bus, 444 .release_bus = stm32_qspi_release_bus, 445 .set_speed = stm32_qspi_set_speed, 446 .set_mode = stm32_qspi_set_mode, 447 .exec_op = stm32_qspi_exec_op, 448 }; 449 450 int stm32_qspi_init(void) 451 { 452 size_t size; 453 int qspi_node; 454 struct dt_node_info info; 455 void *fdt = NULL; 456 int ret; 457 458 if (fdt_get_address(&fdt) == 0) { 459 return -FDT_ERR_NOTFOUND; 460 } 461 462 qspi_node = dt_get_node(&info, -1, DT_QSPI_COMPAT); 463 if (qspi_node < 0) { 464 ERROR("No QSPI ctrl found\n"); 465 return -FDT_ERR_NOTFOUND; 466 } 467 468 if (info.status == DT_DISABLED) { 469 return -FDT_ERR_NOTFOUND; 470 } 471 472 ret = fdt_get_reg_props_by_name(fdt, qspi_node, "qspi", 473 &stm32_qspi.reg_base, &size); 474 if (ret != 0) { 475 return ret; 476 } 477 478 ret = fdt_get_reg_props_by_name(fdt, qspi_node, "qspi_mm", 479 &stm32_qspi.mm_base, 480 &stm32_qspi.mm_size); 481 if (ret != 0) { 482 return ret; 483 } 484 485 if (dt_set_pinctrl_config(qspi_node) != 0) { 486 return -FDT_ERR_BADVALUE; 487 } 488 489 if ((info.clock < 0) || (info.reset < 0)) { 490 return -FDT_ERR_BADVALUE; 491 } 492 493 stm32_qspi.clock_id = (unsigned long)info.clock; 494 stm32_qspi.reset_id = (unsigned int)info.reset; 495 496 stm32mp_clk_enable(stm32_qspi.clock_id); 497 498 ret = stm32mp_reset_assert(stm32_qspi.reset_id, TIMEOUT_US_1_MS); 499 if (ret != 0) { 500 panic(); 501 } 502 ret = stm32mp_reset_deassert(stm32_qspi.reset_id, TIMEOUT_US_1_MS); 503 if (ret != 0) { 504 panic(); 505 } 506 507 mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT); 508 mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK); 509 510 return spi_mem_init_slave(fdt, qspi_node, &stm32_qspi_bus_ops); 511 }; 512