1 /* 2 * Copyright (c) 2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <libfdt.h> 8 9 #include <platform_def.h> 10 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <drivers/spi_mem.h> 14 #include <drivers/st/stm32_gpio.h> 15 #include <drivers/st/stm32mp_reset.h> 16 #include <lib/mmio.h> 17 #include <lib/utils_def.h> 18 19 /* QUADSPI registers */ 20 #define QSPI_CR 0x00U 21 #define QSPI_DCR 0x04U 22 #define QSPI_SR 0x08U 23 #define QSPI_FCR 0x0CU 24 #define QSPI_DLR 0x10U 25 #define QSPI_CCR 0x14U 26 #define QSPI_AR 0x18U 27 #define QSPI_ABR 0x1CU 28 #define QSPI_DR 0x20U 29 #define QSPI_PSMKR 0x24U 30 #define QSPI_PSMAR 0x28U 31 #define QSPI_PIR 0x2CU 32 #define QSPI_LPTR 0x30U 33 34 /* QUADSPI control register */ 35 #define QSPI_CR_EN BIT(0) 36 #define QSPI_CR_ABORT BIT(1) 37 #define QSPI_CR_DMAEN BIT(2) 38 #define QSPI_CR_TCEN BIT(3) 39 #define QSPI_CR_SSHIFT BIT(4) 40 #define QSPI_CR_DFM BIT(6) 41 #define QSPI_CR_FSEL BIT(7) 42 #define QSPI_CR_FTHRES_SHIFT 8U 43 #define QSPI_CR_TEIE BIT(16) 44 #define QSPI_CR_TCIE BIT(17) 45 #define QSPI_CR_FTIE BIT(18) 46 #define QSPI_CR_SMIE BIT(19) 47 #define QSPI_CR_TOIE BIT(20) 48 #define QSPI_CR_APMS BIT(22) 49 #define QSPI_CR_PMM BIT(23) 50 #define QSPI_CR_PRESCALER_MASK GENMASK_32(31, 24) 51 #define QSPI_CR_PRESCALER_SHIFT 24U 52 53 /* QUADSPI device configuration register */ 54 #define QSPI_DCR_CKMODE BIT(0) 55 #define QSPI_DCR_CSHT_MASK GENMASK_32(10, 8) 56 #define QSPI_DCR_CSHT_SHIFT 8U 57 #define QSPI_DCR_FSIZE_MASK GENMASK_32(20, 16) 58 #define QSPI_DCR_FSIZE_SHIFT 16U 59 60 /* QUADSPI status register */ 61 #define QSPI_SR_TEF BIT(0) 62 #define QSPI_SR_TCF BIT(1) 63 #define QSPI_SR_FTF BIT(2) 64 #define QSPI_SR_SMF BIT(3) 65 #define QSPI_SR_TOF BIT(4) 66 #define QSPI_SR_BUSY BIT(5) 67 68 /* QUADSPI flag clear register */ 69 #define QSPI_FCR_CTEF BIT(0) 70 #define QSPI_FCR_CTCF BIT(1) 71 #define QSPI_FCR_CSMF BIT(3) 72 #define QSPI_FCR_CTOF BIT(4) 73 74 /* QUADSPI communication configuration register */ 75 #define QSPI_CCR_DDRM BIT(31) 76 #define QSPI_CCR_DHHC BIT(30) 77 #define QSPI_CCR_SIOO BIT(28) 78 #define QSPI_CCR_FMODE_SHIFT 26U 79 #define QSPI_CCR_DMODE_SHIFT 24U 80 #define QSPI_CCR_DCYC_SHIFT 18U 81 #define QSPI_CCR_ABSIZE_SHIFT 16U 82 #define QSPI_CCR_ABMODE_SHIFT 14U 83 #define QSPI_CCR_ADSIZE_SHIFT 12U 84 #define QSPI_CCR_ADMODE_SHIFT 10U 85 #define QSPI_CCR_IMODE_SHIFT 8U 86 #define QSPI_CCR_IND_WRITE 0U 87 #define QSPI_CCR_IND_READ 1U 88 #define QSPI_CCR_MEM_MAP 3U 89 90 #define QSPI_MAX_CHIP 2U 91 92 #define QSPI_FIFO_TIMEOUT_US 30U 93 #define QSPI_CMD_TIMEOUT_US 1000U 94 #define QSPI_BUSY_TIMEOUT_US 100U 95 #define QSPI_ABT_TIMEOUT_US 100U 96 97 #define DT_QSPI_COMPAT "st,stm32f469-qspi" 98 99 #define FREQ_100MHZ 100000000U 100 101 struct stm32_qspi_ctrl { 102 uintptr_t reg_base; 103 uintptr_t mm_base; 104 size_t mm_size; 105 unsigned long clock_id; 106 unsigned int reset_id; 107 }; 108 109 static struct stm32_qspi_ctrl stm32_qspi; 110 111 static uintptr_t qspi_base(void) 112 { 113 return stm32_qspi.reg_base; 114 } 115 116 static int stm32_qspi_wait_for_not_busy(void) 117 { 118 uint64_t timeout = timeout_init_us(QSPI_BUSY_TIMEOUT_US); 119 120 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) { 121 if (timeout_elapsed(timeout)) { 122 ERROR("%s: busy timeout\n", __func__); 123 return -ETIMEDOUT; 124 } 125 } 126 127 return 0; 128 } 129 130 static int stm32_qspi_wait_cmd(const struct spi_mem_op *op) 131 { 132 int ret = 0; 133 uint64_t timeout; 134 135 if (op->data.nbytes == 0U) { 136 return stm32_qspi_wait_for_not_busy(); 137 } 138 139 timeout = timeout_init_us(QSPI_CMD_TIMEOUT_US); 140 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) { 141 if (timeout_elapsed(timeout)) { 142 ret = -ETIMEDOUT; 143 break; 144 } 145 } 146 147 if (ret == 0) { 148 if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) { 149 ERROR("%s: transfer error\n", __func__); 150 ret = -EIO; 151 } 152 } else { 153 ERROR("%s: cmd timeout\n", __func__); 154 } 155 156 /* Clear flags */ 157 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF); 158 159 return ret; 160 } 161 162 static void stm32_qspi_read_fifo(uint8_t *val, uintptr_t addr) 163 { 164 *val = mmio_read_8(addr); 165 } 166 167 static void stm32_qspi_write_fifo(uint8_t *val, uintptr_t addr) 168 { 169 mmio_write_8(addr, *val); 170 } 171 172 static int stm32_qspi_poll(const struct spi_mem_op *op) 173 { 174 void (*fifo)(uint8_t *val, uintptr_t addr); 175 uint32_t len = op->data.nbytes; 176 uint8_t *buf; 177 uint64_t timeout; 178 179 if (op->data.dir == SPI_MEM_DATA_IN) { 180 fifo = stm32_qspi_read_fifo; 181 } else { 182 fifo = stm32_qspi_write_fifo; 183 } 184 185 buf = (uint8_t *)op->data.buf; 186 187 for (len = op->data.nbytes; len != 0U; len--) { 188 timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US); 189 while ((mmio_read_32(qspi_base() + QSPI_SR) & 190 QSPI_SR_FTF) == 0U) { 191 if (timeout_elapsed(timeout)) { 192 ERROR("%s: fifo timeout\n", __func__); 193 return -ETIMEDOUT; 194 } 195 } 196 197 fifo(buf++, qspi_base() + QSPI_DR); 198 } 199 200 return 0; 201 } 202 203 static int stm32_qspi_mm(const struct spi_mem_op *op) 204 { 205 memcpy(op->data.buf, 206 (void *)(stm32_qspi.mm_base + (size_t)op->addr.val), 207 op->data.nbytes); 208 209 return 0; 210 } 211 212 static int stm32_qspi_tx(const struct spi_mem_op *op, uint8_t mode) 213 { 214 if (op->data.nbytes == 0U) { 215 return 0; 216 } 217 218 if (mode == QSPI_CCR_MEM_MAP) { 219 return stm32_qspi_mm(op); 220 } 221 222 return stm32_qspi_poll(op); 223 } 224 225 static unsigned int stm32_qspi_get_mode(uint8_t buswidth) 226 { 227 if (buswidth == 4U) { 228 return 3U; 229 } 230 231 return buswidth; 232 } 233 234 static int stm32_qspi_exec_op(const struct spi_mem_op *op) 235 { 236 uint64_t timeout; 237 uint32_t ccr; 238 size_t addr_max; 239 uint8_t mode = QSPI_CCR_IND_WRITE; 240 int ret; 241 242 VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addr:%llx len:%x\n", 243 __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 244 op->dummy.buswidth, op->data.buswidth, 245 op->addr.val, op->data.nbytes); 246 247 ret = stm32_qspi_wait_for_not_busy(); 248 if (ret != 0) { 249 return ret; 250 } 251 252 addr_max = op->addr.val + op->data.nbytes + 1U; 253 254 if ((op->data.dir == SPI_MEM_DATA_IN) && (op->data.nbytes != 0U)) { 255 if ((addr_max < stm32_qspi.mm_size) && 256 (op->addr.buswidth != 0U)) { 257 mode = QSPI_CCR_MEM_MAP; 258 } else { 259 mode = QSPI_CCR_IND_READ; 260 } 261 } 262 263 if (op->data.nbytes != 0U) { 264 mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U); 265 } 266 267 ccr = mode << QSPI_CCR_FMODE_SHIFT; 268 ccr |= op->cmd.opcode; 269 ccr |= stm32_qspi_get_mode(op->cmd.buswidth) << QSPI_CCR_IMODE_SHIFT; 270 271 if (op->addr.nbytes != 0U) { 272 ccr |= (op->addr.nbytes - 1U) << QSPI_CCR_ADSIZE_SHIFT; 273 ccr |= stm32_qspi_get_mode(op->addr.buswidth) << 274 QSPI_CCR_ADMODE_SHIFT; 275 } 276 277 if ((op->dummy.buswidth != 0U) && (op->dummy.nbytes != 0U)) { 278 ccr |= (op->dummy.nbytes * 8U / op->dummy.buswidth) << 279 QSPI_CCR_DCYC_SHIFT; 280 } 281 282 if (op->data.nbytes != 0U) { 283 ccr |= stm32_qspi_get_mode(op->data.buswidth) << 284 QSPI_CCR_DMODE_SHIFT; 285 } 286 287 mmio_write_32(qspi_base() + QSPI_CCR, ccr); 288 289 if ((op->addr.nbytes != 0U) && (mode != QSPI_CCR_MEM_MAP)) { 290 mmio_write_32(qspi_base() + QSPI_AR, op->addr.val); 291 } 292 293 ret = stm32_qspi_tx(op, mode); 294 295 /* 296 * Abort in: 297 * - Error case. 298 * - Memory mapped read: prefetching must be stopped if we read the last 299 * byte of device (device size - fifo size). If device size is not 300 * known then prefetching is always stopped. 301 */ 302 if ((ret != 0) || (mode == QSPI_CCR_MEM_MAP)) { 303 goto abort; 304 } 305 306 /* Wait end of TX in indirect mode */ 307 ret = stm32_qspi_wait_cmd(op); 308 if (ret != 0) { 309 goto abort; 310 } 311 312 return 0; 313 314 abort: 315 mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT); 316 317 /* Wait clear of abort bit by hardware */ 318 timeout = timeout_init_us(QSPI_ABT_TIMEOUT_US); 319 while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) { 320 if (timeout_elapsed(timeout)) { 321 ret = -ETIMEDOUT; 322 break; 323 } 324 } 325 326 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF); 327 328 if (ret != 0) { 329 ERROR("%s: exec op error\n", __func__); 330 } 331 332 return ret; 333 } 334 335 static int stm32_qspi_claim_bus(unsigned int cs) 336 { 337 uint32_t cr; 338 339 if (cs >= QSPI_MAX_CHIP) { 340 return -ENODEV; 341 } 342 343 /* Set chip select and enable the controller */ 344 cr = QSPI_CR_EN; 345 if (cs == 1U) { 346 cr |= QSPI_CR_FSEL; 347 } 348 349 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr); 350 351 return 0; 352 } 353 354 static void stm32_qspi_release_bus(void) 355 { 356 mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN); 357 } 358 359 static int stm32_qspi_set_speed(unsigned int hz) 360 { 361 unsigned long qspi_clk = stm32mp_clk_get_rate(stm32_qspi.clock_id); 362 uint32_t prescaler = UINT8_MAX; 363 uint32_t csht; 364 int ret; 365 366 if (qspi_clk == 0U) { 367 return -EINVAL; 368 } 369 370 if (hz > 0U) { 371 prescaler = div_round_up(qspi_clk, hz) - 1U; 372 if (prescaler > UINT8_MAX) { 373 prescaler = UINT8_MAX; 374 } 375 } 376 377 csht = div_round_up((5U * qspi_clk) / (prescaler + 1U), FREQ_100MHZ); 378 csht = ((csht - 1U) << QSPI_DCR_CSHT_SHIFT) & QSPI_DCR_CSHT_MASK; 379 380 ret = stm32_qspi_wait_for_not_busy(); 381 if (ret != 0) { 382 return ret; 383 } 384 385 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK, 386 prescaler << QSPI_CR_PRESCALER_SHIFT); 387 388 mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht); 389 390 VERBOSE("%s: speed=%lu\n", __func__, qspi_clk / (prescaler + 1U)); 391 392 return 0; 393 } 394 395 static int stm32_qspi_set_mode(unsigned int mode) 396 { 397 int ret; 398 399 ret = stm32_qspi_wait_for_not_busy(); 400 if (ret != 0) { 401 return ret; 402 } 403 404 if ((mode & SPI_CS_HIGH) != 0U) { 405 return -ENODEV; 406 } 407 408 if (((mode & SPI_CPHA) != 0U) && ((mode & SPI_CPOL) != 0U)) { 409 mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); 410 } else if (((mode & SPI_CPHA) == 0U) && ((mode & SPI_CPOL) == 0U)) { 411 mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); 412 } else { 413 return -ENODEV; 414 } 415 416 VERBOSE("%s: mode=0x%x\n", __func__, mode); 417 418 if ((mode & SPI_RX_QUAD) != 0U) { 419 VERBOSE("rx: quad\n"); 420 } else if ((mode & SPI_RX_DUAL) != 0U) { 421 VERBOSE("rx: dual\n"); 422 } else { 423 VERBOSE("rx: single\n"); 424 } 425 426 if ((mode & SPI_TX_QUAD) != 0U) { 427 VERBOSE("tx: quad\n"); 428 } else if ((mode & SPI_TX_DUAL) != 0U) { 429 VERBOSE("tx: dual\n"); 430 } else { 431 VERBOSE("tx: single\n"); 432 } 433 434 return 0; 435 } 436 437 static const struct spi_bus_ops stm32_qspi_bus_ops = { 438 .claim_bus = stm32_qspi_claim_bus, 439 .release_bus = stm32_qspi_release_bus, 440 .set_speed = stm32_qspi_set_speed, 441 .set_mode = stm32_qspi_set_mode, 442 .exec_op = stm32_qspi_exec_op, 443 }; 444 445 int stm32_qspi_init(void) 446 { 447 size_t size; 448 int qspi_node; 449 struct dt_node_info info; 450 void *fdt = NULL; 451 int ret; 452 453 if (fdt_get_address(&fdt) == 0) { 454 return -FDT_ERR_NOTFOUND; 455 } 456 457 qspi_node = dt_get_node(&info, -1, DT_QSPI_COMPAT); 458 if (qspi_node < 0) { 459 ERROR("No QSPI ctrl found\n"); 460 return -FDT_ERR_NOTFOUND; 461 } 462 463 if (info.status == DT_DISABLED) { 464 return -FDT_ERR_NOTFOUND; 465 } 466 467 ret = fdt_get_reg_props_by_name(qspi_node, "qspi", 468 &stm32_qspi.reg_base, &size); 469 if (ret != 0) { 470 return ret; 471 } 472 473 ret = fdt_get_reg_props_by_name(qspi_node, "qspi_mm", 474 &stm32_qspi.mm_base, 475 &stm32_qspi.mm_size); 476 if (ret != 0) { 477 return ret; 478 } 479 480 if (dt_set_pinctrl_config(qspi_node) != 0) { 481 return -FDT_ERR_BADVALUE; 482 } 483 484 if ((info.clock < 0) || (info.reset < 0)) { 485 return -FDT_ERR_BADVALUE; 486 } 487 488 stm32_qspi.clock_id = (unsigned long)info.clock; 489 stm32_qspi.reset_id = (unsigned int)info.reset; 490 491 stm32mp_clk_enable(stm32_qspi.clock_id); 492 493 stm32mp_reset_assert(stm32_qspi.reset_id); 494 stm32mp_reset_deassert(stm32_qspi.reset_id); 495 496 mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT); 497 mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK); 498 499 return spi_mem_init_slave(fdt, qspi_node, &stm32_qspi_bus_ops); 500 }; 501