1 /* 2 * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <libfdt.h> 8 9 #include <platform_def.h> 10 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <drivers/spi_mem.h> 14 #include <drivers/st/stm32_gpio.h> 15 #include <drivers/st/stm32_qspi.h> 16 #include <drivers/st/stm32mp_reset.h> 17 #include <lib/mmio.h> 18 #include <lib/utils_def.h> 19 20 /* QUADSPI registers */ 21 #define QSPI_CR 0x00U 22 #define QSPI_DCR 0x04U 23 #define QSPI_SR 0x08U 24 #define QSPI_FCR 0x0CU 25 #define QSPI_DLR 0x10U 26 #define QSPI_CCR 0x14U 27 #define QSPI_AR 0x18U 28 #define QSPI_ABR 0x1CU 29 #define QSPI_DR 0x20U 30 #define QSPI_PSMKR 0x24U 31 #define QSPI_PSMAR 0x28U 32 #define QSPI_PIR 0x2CU 33 #define QSPI_LPTR 0x30U 34 35 /* QUADSPI control register */ 36 #define QSPI_CR_EN BIT(0) 37 #define QSPI_CR_ABORT BIT(1) 38 #define QSPI_CR_DMAEN BIT(2) 39 #define QSPI_CR_TCEN BIT(3) 40 #define QSPI_CR_SSHIFT BIT(4) 41 #define QSPI_CR_DFM BIT(6) 42 #define QSPI_CR_FSEL BIT(7) 43 #define QSPI_CR_FTHRES_SHIFT 8U 44 #define QSPI_CR_TEIE BIT(16) 45 #define QSPI_CR_TCIE BIT(17) 46 #define QSPI_CR_FTIE BIT(18) 47 #define QSPI_CR_SMIE BIT(19) 48 #define QSPI_CR_TOIE BIT(20) 49 #define QSPI_CR_APMS BIT(22) 50 #define QSPI_CR_PMM BIT(23) 51 #define QSPI_CR_PRESCALER_MASK GENMASK_32(31, 24) 52 #define QSPI_CR_PRESCALER_SHIFT 24U 53 54 /* QUADSPI device configuration register */ 55 #define QSPI_DCR_CKMODE BIT(0) 56 #define QSPI_DCR_CSHT_MASK GENMASK_32(10, 8) 57 #define QSPI_DCR_CSHT_SHIFT 8U 58 #define QSPI_DCR_FSIZE_MASK GENMASK_32(20, 16) 59 #define QSPI_DCR_FSIZE_SHIFT 16U 60 61 /* QUADSPI status register */ 62 #define QSPI_SR_TEF BIT(0) 63 #define QSPI_SR_TCF BIT(1) 64 #define QSPI_SR_FTF BIT(2) 65 #define QSPI_SR_SMF BIT(3) 66 #define QSPI_SR_TOF BIT(4) 67 #define QSPI_SR_BUSY BIT(5) 68 69 /* QUADSPI flag clear register */ 70 #define QSPI_FCR_CTEF BIT(0) 71 #define QSPI_FCR_CTCF BIT(1) 72 #define QSPI_FCR_CSMF BIT(3) 73 #define QSPI_FCR_CTOF BIT(4) 74 75 /* QUADSPI communication configuration register */ 76 #define QSPI_CCR_DDRM BIT(31) 77 #define QSPI_CCR_DHHC BIT(30) 78 #define QSPI_CCR_SIOO BIT(28) 79 #define QSPI_CCR_FMODE_SHIFT 26U 80 #define QSPI_CCR_DMODE_SHIFT 24U 81 #define QSPI_CCR_DCYC_SHIFT 18U 82 #define QSPI_CCR_ABSIZE_SHIFT 16U 83 #define QSPI_CCR_ABMODE_SHIFT 14U 84 #define QSPI_CCR_ADSIZE_SHIFT 12U 85 #define QSPI_CCR_ADMODE_SHIFT 10U 86 #define QSPI_CCR_IMODE_SHIFT 8U 87 #define QSPI_CCR_IND_WRITE 0U 88 #define QSPI_CCR_IND_READ 1U 89 #define QSPI_CCR_MEM_MAP 3U 90 91 #define QSPI_MAX_CHIP 2U 92 93 #define QSPI_FIFO_TIMEOUT_US 30U 94 #define QSPI_CMD_TIMEOUT_US 1000U 95 #define QSPI_BUSY_TIMEOUT_US 100U 96 #define QSPI_ABT_TIMEOUT_US 100U 97 98 #define DT_QSPI_COMPAT "st,stm32f469-qspi" 99 100 #define FREQ_100MHZ 100000000U 101 102 struct stm32_qspi_ctrl { 103 uintptr_t reg_base; 104 uintptr_t mm_base; 105 size_t mm_size; 106 unsigned long clock_id; 107 unsigned int reset_id; 108 }; 109 110 static struct stm32_qspi_ctrl stm32_qspi; 111 112 static uintptr_t qspi_base(void) 113 { 114 return stm32_qspi.reg_base; 115 } 116 117 static int stm32_qspi_wait_for_not_busy(void) 118 { 119 uint64_t timeout = timeout_init_us(QSPI_BUSY_TIMEOUT_US); 120 121 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) { 122 if (timeout_elapsed(timeout)) { 123 ERROR("%s: busy timeout\n", __func__); 124 return -ETIMEDOUT; 125 } 126 } 127 128 return 0; 129 } 130 131 static int stm32_qspi_wait_cmd(const struct spi_mem_op *op) 132 { 133 int ret = 0; 134 uint64_t timeout; 135 136 if (op->data.nbytes == 0U) { 137 return stm32_qspi_wait_for_not_busy(); 138 } 139 140 timeout = timeout_init_us(QSPI_CMD_TIMEOUT_US); 141 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) { 142 if (timeout_elapsed(timeout)) { 143 ret = -ETIMEDOUT; 144 break; 145 } 146 } 147 148 if (ret == 0) { 149 if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) { 150 ERROR("%s: transfer error\n", __func__); 151 ret = -EIO; 152 } 153 } else { 154 ERROR("%s: cmd timeout\n", __func__); 155 } 156 157 /* Clear flags */ 158 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF); 159 160 return ret; 161 } 162 163 static void stm32_qspi_read_fifo(uint8_t *val, uintptr_t addr) 164 { 165 *val = mmio_read_8(addr); 166 } 167 168 static void stm32_qspi_write_fifo(uint8_t *val, uintptr_t addr) 169 { 170 mmio_write_8(addr, *val); 171 } 172 173 static int stm32_qspi_poll(const struct spi_mem_op *op) 174 { 175 void (*fifo)(uint8_t *val, uintptr_t addr); 176 uint32_t len; 177 uint8_t *buf; 178 179 if (op->data.dir == SPI_MEM_DATA_IN) { 180 fifo = stm32_qspi_read_fifo; 181 } else { 182 fifo = stm32_qspi_write_fifo; 183 } 184 185 buf = (uint8_t *)op->data.buf; 186 187 for (len = op->data.nbytes; len != 0U; len--) { 188 uint64_t timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US); 189 190 while ((mmio_read_32(qspi_base() + QSPI_SR) & 191 QSPI_SR_FTF) == 0U) { 192 if (timeout_elapsed(timeout)) { 193 ERROR("%s: fifo timeout\n", __func__); 194 return -ETIMEDOUT; 195 } 196 } 197 198 fifo(buf++, qspi_base() + QSPI_DR); 199 } 200 201 return 0; 202 } 203 204 static int stm32_qspi_mm(const struct spi_mem_op *op) 205 { 206 memcpy(op->data.buf, 207 (void *)(stm32_qspi.mm_base + (size_t)op->addr.val), 208 op->data.nbytes); 209 210 return 0; 211 } 212 213 static int stm32_qspi_tx(const struct spi_mem_op *op, uint8_t mode) 214 { 215 if (op->data.nbytes == 0U) { 216 return 0; 217 } 218 219 if (mode == QSPI_CCR_MEM_MAP) { 220 return stm32_qspi_mm(op); 221 } 222 223 return stm32_qspi_poll(op); 224 } 225 226 static unsigned int stm32_qspi_get_mode(uint8_t buswidth) 227 { 228 if (buswidth == 4U) { 229 return 3U; 230 } 231 232 return buswidth; 233 } 234 235 static int stm32_qspi_exec_op(const struct spi_mem_op *op) 236 { 237 uint64_t timeout; 238 uint32_t ccr; 239 size_t addr_max; 240 uint8_t mode = QSPI_CCR_IND_WRITE; 241 int ret; 242 243 VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addr:%llx len:%x\n", 244 __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 245 op->dummy.buswidth, op->data.buswidth, 246 op->addr.val, op->data.nbytes); 247 248 ret = stm32_qspi_wait_for_not_busy(); 249 if (ret != 0) { 250 return ret; 251 } 252 253 addr_max = op->addr.val + op->data.nbytes + 1U; 254 255 if ((op->data.dir == SPI_MEM_DATA_IN) && (op->data.nbytes != 0U)) { 256 if ((addr_max < stm32_qspi.mm_size) && 257 (op->addr.buswidth != 0U)) { 258 mode = QSPI_CCR_MEM_MAP; 259 } else { 260 mode = QSPI_CCR_IND_READ; 261 } 262 } 263 264 if (op->data.nbytes != 0U) { 265 mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U); 266 } 267 268 ccr = mode << QSPI_CCR_FMODE_SHIFT; 269 ccr |= op->cmd.opcode; 270 ccr |= stm32_qspi_get_mode(op->cmd.buswidth) << QSPI_CCR_IMODE_SHIFT; 271 272 if (op->addr.nbytes != 0U) { 273 ccr |= (op->addr.nbytes - 1U) << QSPI_CCR_ADSIZE_SHIFT; 274 ccr |= stm32_qspi_get_mode(op->addr.buswidth) << 275 QSPI_CCR_ADMODE_SHIFT; 276 } 277 278 if ((op->dummy.buswidth != 0U) && (op->dummy.nbytes != 0U)) { 279 ccr |= (op->dummy.nbytes * 8U / op->dummy.buswidth) << 280 QSPI_CCR_DCYC_SHIFT; 281 } 282 283 if (op->data.nbytes != 0U) { 284 ccr |= stm32_qspi_get_mode(op->data.buswidth) << 285 QSPI_CCR_DMODE_SHIFT; 286 } 287 288 mmio_write_32(qspi_base() + QSPI_CCR, ccr); 289 290 if ((op->addr.nbytes != 0U) && (mode != QSPI_CCR_MEM_MAP)) { 291 mmio_write_32(qspi_base() + QSPI_AR, op->addr.val); 292 } 293 294 ret = stm32_qspi_tx(op, mode); 295 296 /* 297 * Abort in: 298 * - Error case. 299 * - Memory mapped read: prefetching must be stopped if we read the last 300 * byte of device (device size - fifo size). If device size is not 301 * known then prefetching is always stopped. 302 */ 303 if ((ret != 0) || (mode == QSPI_CCR_MEM_MAP)) { 304 goto abort; 305 } 306 307 /* Wait end of TX in indirect mode */ 308 ret = stm32_qspi_wait_cmd(op); 309 if (ret != 0) { 310 goto abort; 311 } 312 313 return 0; 314 315 abort: 316 mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT); 317 318 /* Wait clear of abort bit by hardware */ 319 timeout = timeout_init_us(QSPI_ABT_TIMEOUT_US); 320 while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) { 321 if (timeout_elapsed(timeout)) { 322 ret = -ETIMEDOUT; 323 break; 324 } 325 } 326 327 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF); 328 329 if (ret != 0) { 330 ERROR("%s: exec op error\n", __func__); 331 } 332 333 return ret; 334 } 335 336 static int stm32_qspi_claim_bus(unsigned int cs) 337 { 338 uint32_t cr; 339 340 if (cs >= QSPI_MAX_CHIP) { 341 return -ENODEV; 342 } 343 344 /* Set chip select and enable the controller */ 345 cr = QSPI_CR_EN; 346 if (cs == 1U) { 347 cr |= QSPI_CR_FSEL; 348 } 349 350 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr); 351 352 return 0; 353 } 354 355 static void stm32_qspi_release_bus(void) 356 { 357 mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN); 358 } 359 360 static int stm32_qspi_set_speed(unsigned int hz) 361 { 362 unsigned long qspi_clk = stm32mp_clk_get_rate(stm32_qspi.clock_id); 363 uint32_t prescaler = UINT8_MAX; 364 uint32_t csht; 365 int ret; 366 367 if (qspi_clk == 0U) { 368 return -EINVAL; 369 } 370 371 if (hz > 0U) { 372 prescaler = div_round_up(qspi_clk, hz) - 1U; 373 if (prescaler > UINT8_MAX) { 374 prescaler = UINT8_MAX; 375 } 376 } 377 378 csht = div_round_up((5U * qspi_clk) / (prescaler + 1U), FREQ_100MHZ); 379 csht = ((csht - 1U) << QSPI_DCR_CSHT_SHIFT) & QSPI_DCR_CSHT_MASK; 380 381 ret = stm32_qspi_wait_for_not_busy(); 382 if (ret != 0) { 383 return ret; 384 } 385 386 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK, 387 prescaler << QSPI_CR_PRESCALER_SHIFT); 388 389 mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht); 390 391 VERBOSE("%s: speed=%lu\n", __func__, qspi_clk / (prescaler + 1U)); 392 393 return 0; 394 } 395 396 static int stm32_qspi_set_mode(unsigned int mode) 397 { 398 int ret; 399 400 ret = stm32_qspi_wait_for_not_busy(); 401 if (ret != 0) { 402 return ret; 403 } 404 405 if ((mode & SPI_CS_HIGH) != 0U) { 406 return -ENODEV; 407 } 408 409 if (((mode & SPI_CPHA) != 0U) && ((mode & SPI_CPOL) != 0U)) { 410 mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); 411 } else if (((mode & SPI_CPHA) == 0U) && ((mode & SPI_CPOL) == 0U)) { 412 mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); 413 } else { 414 return -ENODEV; 415 } 416 417 VERBOSE("%s: mode=0x%x\n", __func__, mode); 418 419 if ((mode & SPI_RX_QUAD) != 0U) { 420 VERBOSE("rx: quad\n"); 421 } else if ((mode & SPI_RX_DUAL) != 0U) { 422 VERBOSE("rx: dual\n"); 423 } else { 424 VERBOSE("rx: single\n"); 425 } 426 427 if ((mode & SPI_TX_QUAD) != 0U) { 428 VERBOSE("tx: quad\n"); 429 } else if ((mode & SPI_TX_DUAL) != 0U) { 430 VERBOSE("tx: dual\n"); 431 } else { 432 VERBOSE("tx: single\n"); 433 } 434 435 return 0; 436 } 437 438 static const struct spi_bus_ops stm32_qspi_bus_ops = { 439 .claim_bus = stm32_qspi_claim_bus, 440 .release_bus = stm32_qspi_release_bus, 441 .set_speed = stm32_qspi_set_speed, 442 .set_mode = stm32_qspi_set_mode, 443 .exec_op = stm32_qspi_exec_op, 444 }; 445 446 int stm32_qspi_init(void) 447 { 448 size_t size; 449 int qspi_node; 450 struct dt_node_info info; 451 void *fdt = NULL; 452 int ret; 453 454 if (fdt_get_address(&fdt) == 0) { 455 return -FDT_ERR_NOTFOUND; 456 } 457 458 qspi_node = dt_get_node(&info, -1, DT_QSPI_COMPAT); 459 if (qspi_node < 0) { 460 ERROR("No QSPI ctrl found\n"); 461 return -FDT_ERR_NOTFOUND; 462 } 463 464 if (info.status == DT_DISABLED) { 465 return -FDT_ERR_NOTFOUND; 466 } 467 468 ret = fdt_get_reg_props_by_name(qspi_node, "qspi", 469 &stm32_qspi.reg_base, &size); 470 if (ret != 0) { 471 return ret; 472 } 473 474 ret = fdt_get_reg_props_by_name(qspi_node, "qspi_mm", 475 &stm32_qspi.mm_base, 476 &stm32_qspi.mm_size); 477 if (ret != 0) { 478 return ret; 479 } 480 481 if (dt_set_pinctrl_config(qspi_node) != 0) { 482 return -FDT_ERR_BADVALUE; 483 } 484 485 if ((info.clock < 0) || (info.reset < 0)) { 486 return -FDT_ERR_BADVALUE; 487 } 488 489 stm32_qspi.clock_id = (unsigned long)info.clock; 490 stm32_qspi.reset_id = (unsigned int)info.reset; 491 492 stm32mp_clk_enable(stm32_qspi.clock_id); 493 494 stm32mp_reset_assert(stm32_qspi.reset_id); 495 stm32mp_reset_deassert(stm32_qspi.reset_id); 496 497 mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT); 498 mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK); 499 500 return spi_mem_init_slave(fdt, qspi_node, &stm32_qspi_bus_ops); 501 }; 502