1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 #include <drivers/st/stm32mp1_clkfunc.h> 21 #include <drivers/st/stm32mp1_rcc.h> 22 #include <dt-bindings/clock/stm32mp1-clks.h> 23 #include <dt-bindings/clock/stm32mp1-clksrc.h> 24 #include <lib/mmio.h> 25 #include <lib/utils_def.h> 26 #include <plat/common/platform.h> 27 28 #include <stm32mp1_dt.h> 29 #include <stm32mp1_private.h> 30 31 #define MAX_HSI_HZ 64000000 32 33 #define TIMEOUT_200MS (plat_get_syscnt_freq2() / 5U) 34 #define TIMEOUT_1S plat_get_syscnt_freq2() 35 36 #define PLLRDY_TIMEOUT TIMEOUT_200MS 37 #define CLKSRC_TIMEOUT TIMEOUT_200MS 38 #define CLKDIV_TIMEOUT TIMEOUT_200MS 39 #define HSIDIV_TIMEOUT TIMEOUT_200MS 40 #define OSCRDY_TIMEOUT TIMEOUT_1S 41 42 enum stm32mp1_parent_id { 43 /* Oscillators are defined in enum stm32mp_osc_id */ 44 45 /* Other parent source */ 46 _HSI_KER = NB_OSC, 47 _HSE_KER, 48 _HSE_KER_DIV2, 49 _CSI_KER, 50 _PLL1_P, 51 _PLL1_Q, 52 _PLL1_R, 53 _PLL2_P, 54 _PLL2_Q, 55 _PLL2_R, 56 _PLL3_P, 57 _PLL3_Q, 58 _PLL3_R, 59 _PLL4_P, 60 _PLL4_Q, 61 _PLL4_R, 62 _ACLK, 63 _PCLK1, 64 _PCLK2, 65 _PCLK3, 66 _PCLK4, 67 _PCLK5, 68 _HCLK6, 69 _HCLK2, 70 _CK_PER, 71 _CK_MPU, 72 _PARENT_NB, 73 _UNKNOWN_ID = 0xff, 74 }; 75 76 enum stm32mp1_parent_sel { 77 _I2C46_SEL, 78 _UART6_SEL, 79 _UART24_SEL, 80 _UART35_SEL, 81 _UART78_SEL, 82 _SDMMC12_SEL, 83 _SDMMC3_SEL, 84 _QSPI_SEL, 85 _FMC_SEL, 86 _USBPHY_SEL, 87 _USBO_SEL, 88 _STGEN_SEL, 89 _PARENT_SEL_NB, 90 _UNKNOWN_SEL = 0xff, 91 }; 92 93 enum stm32mp1_pll_id { 94 _PLL1, 95 _PLL2, 96 _PLL3, 97 _PLL4, 98 _PLL_NB 99 }; 100 101 enum stm32mp1_div_id { 102 _DIV_P, 103 _DIV_Q, 104 _DIV_R, 105 _DIV_NB, 106 }; 107 108 enum stm32mp1_clksrc_id { 109 CLKSRC_MPU, 110 CLKSRC_AXI, 111 CLKSRC_PLL12, 112 CLKSRC_PLL3, 113 CLKSRC_PLL4, 114 CLKSRC_RTC, 115 CLKSRC_MCO1, 116 CLKSRC_MCO2, 117 CLKSRC_NB 118 }; 119 120 enum stm32mp1_clkdiv_id { 121 CLKDIV_MPU, 122 CLKDIV_AXI, 123 CLKDIV_APB1, 124 CLKDIV_APB2, 125 CLKDIV_APB3, 126 CLKDIV_APB4, 127 CLKDIV_APB5, 128 CLKDIV_RTC, 129 CLKDIV_MCO1, 130 CLKDIV_MCO2, 131 CLKDIV_NB 132 }; 133 134 enum stm32mp1_pllcfg { 135 PLLCFG_M, 136 PLLCFG_N, 137 PLLCFG_P, 138 PLLCFG_Q, 139 PLLCFG_R, 140 PLLCFG_O, 141 PLLCFG_NB 142 }; 143 144 enum stm32mp1_pllcsg { 145 PLLCSG_MOD_PER, 146 PLLCSG_INC_STEP, 147 PLLCSG_SSCG_MODE, 148 PLLCSG_NB 149 }; 150 151 enum stm32mp1_plltype { 152 PLL_800, 153 PLL_1600, 154 PLL_TYPE_NB 155 }; 156 157 struct stm32mp1_pll { 158 uint8_t refclk_min; 159 uint8_t refclk_max; 160 uint8_t divn_max; 161 }; 162 163 struct stm32mp1_clk_gate { 164 uint16_t offset; 165 uint8_t bit; 166 uint8_t index; 167 uint8_t set_clr; 168 enum stm32mp1_parent_sel sel; 169 enum stm32mp1_parent_id fixed; 170 bool secure; 171 }; 172 173 struct stm32mp1_clk_sel { 174 uint16_t offset; 175 uint8_t src; 176 uint8_t msk; 177 uint8_t nb_parent; 178 const uint8_t *parent; 179 }; 180 181 #define REFCLK_SIZE 4 182 struct stm32mp1_clk_pll { 183 enum stm32mp1_plltype plltype; 184 uint16_t rckxselr; 185 uint16_t pllxcfgr1; 186 uint16_t pllxcfgr2; 187 uint16_t pllxfracr; 188 uint16_t pllxcr; 189 uint16_t pllxcsgr; 190 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 191 }; 192 193 struct stm32mp1_clk_data { 194 const struct stm32mp1_clk_gate *gate; 195 const struct stm32mp1_clk_sel *sel; 196 const struct stm32mp1_clk_pll *pll; 197 const int nb_gate; 198 }; 199 200 struct stm32mp1_clk_priv { 201 uint32_t base; 202 const struct stm32mp1_clk_data *data; 203 unsigned long osc[NB_OSC]; 204 uint32_t pkcs_usb_value; 205 }; 206 207 #define STM32MP1_CLK(off, b, idx, s) \ 208 { \ 209 .offset = (off), \ 210 .bit = (b), \ 211 .index = (idx), \ 212 .set_clr = 0, \ 213 .sel = (s), \ 214 .fixed = _UNKNOWN_ID, \ 215 .secure = 0, \ 216 } 217 218 #define STM32MP1_CLK_F(off, b, idx, f) \ 219 { \ 220 .offset = (off), \ 221 .bit = (b), \ 222 .index = (idx), \ 223 .set_clr = 0, \ 224 .sel = _UNKNOWN_SEL, \ 225 .fixed = (f), \ 226 .secure = 0, \ 227 } 228 229 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ 230 { \ 231 .offset = (off), \ 232 .bit = (b), \ 233 .index = (idx), \ 234 .set_clr = 1, \ 235 .sel = (s), \ 236 .fixed = _UNKNOWN_ID, \ 237 .secure = 0, \ 238 } 239 240 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ 241 { \ 242 .offset = (off), \ 243 .bit = (b), \ 244 .index = (idx), \ 245 .set_clr = 1, \ 246 .sel = _UNKNOWN_SEL, \ 247 .fixed = (f), \ 248 .secure = 0, \ 249 } 250 251 #define STM32MP1_CLK_SEC_SET_CLR(off, b, idx, s) \ 252 { \ 253 .offset = (off), \ 254 .bit = (b), \ 255 .index = (idx), \ 256 .set_clr = 1, \ 257 .sel = (s), \ 258 .fixed = _UNKNOWN_ID, \ 259 .secure = 1, \ 260 } 261 262 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ 263 [(idx)] = { \ 264 .offset = (off), \ 265 .src = (s), \ 266 .msk = (m), \ 267 .parent = (p), \ 268 .nb_parent = ARRAY_SIZE((p)) \ 269 } 270 271 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, \ 272 off4, off5, off6, \ 273 p1, p2, p3, p4) \ 274 [(idx)] = { \ 275 .plltype = (type), \ 276 .rckxselr = (off1), \ 277 .pllxcfgr1 = (off2), \ 278 .pllxcfgr2 = (off3), \ 279 .pllxfracr = (off4), \ 280 .pllxcr = (off5), \ 281 .pllxcsgr = (off6), \ 282 .refclk[0] = (p1), \ 283 .refclk[1] = (p2), \ 284 .refclk[2] = (p3), \ 285 .refclk[3] = (p4), \ 286 } 287 288 static const uint8_t stm32mp1_clks[][2] = { 289 {CK_PER, _CK_PER}, 290 {CK_MPU, _CK_MPU}, 291 {CK_AXI, _ACLK}, 292 {CK_HSE, _HSE}, 293 {CK_CSI, _CSI}, 294 {CK_LSI, _LSI}, 295 {CK_LSE, _LSE}, 296 {CK_HSI, _HSI}, 297 {CK_HSE_DIV2, _HSE_KER_DIV2}, 298 }; 299 300 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 301 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), 302 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), 303 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), 304 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), 305 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 306 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), 307 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), 308 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), 309 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), 310 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), 311 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), 312 313 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 314 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 315 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 316 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 317 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 318 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 319 320 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 321 322 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 323 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 324 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 325 326 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 327 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 328 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 11, TZC1, _UNKNOWN_SEL), 329 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 12, TZC2, _UNKNOWN_SEL), 330 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 331 332 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 333 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 334 335 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 336 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 337 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 338 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 339 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 340 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 341 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 342 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 343 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 344 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 345 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 346 347 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), 348 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 5, HASH1, _UNKNOWN_SEL), 349 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _CSI_KER), 350 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _UNKNOWN_SEL), 351 352 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 353 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 354 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 355 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 356 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 357 358 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 359 }; 360 361 static const uint8_t i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; 362 static const uint8_t uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, 363 _HSE_KER}; 364 static const uint8_t uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 365 _HSE_KER}; 366 static const uint8_t uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 367 _HSE_KER}; 368 static const uint8_t uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 369 _HSE_KER}; 370 static const uint8_t sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; 371 static const uint8_t sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; 372 static const uint8_t qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 373 static const uint8_t fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 374 static const uint8_t usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; 375 static const uint8_t usbo_parents[] = {_PLL4_R, _USB_PHY_48}; 376 static const uint8_t stgen_parents[] = {_HSI_KER, _HSE_KER}; 377 378 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 379 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 380 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 381 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, 382 uart24_parents), 383 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, 384 uart35_parents), 385 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, 386 uart78_parents), 387 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, 388 sdmmc12_parents), 389 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, 390 sdmmc3_parents), 391 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), 392 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), 393 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), 394 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), 395 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 396 }; 397 398 /* Define characteristic of PLL according type */ 399 #define DIVN_MIN 24 400 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 401 [PLL_800] = { 402 .refclk_min = 4, 403 .refclk_max = 16, 404 .divn_max = 99, 405 }, 406 [PLL_1600] = { 407 .refclk_min = 8, 408 .refclk_max = 16, 409 .divn_max = 199, 410 }, 411 }; 412 413 /* PLLNCFGR2 register divider by output */ 414 static const uint8_t pllncfgr2[_DIV_NB] = { 415 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 416 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 417 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT 418 }; 419 420 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 421 STM32MP1_CLK_PLL(_PLL1, PLL_1600, 422 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 423 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 424 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 425 STM32MP1_CLK_PLL(_PLL2, PLL_1600, 426 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 427 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 428 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 429 STM32MP1_CLK_PLL(_PLL3, PLL_800, 430 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 431 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 432 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 433 STM32MP1_CLK_PLL(_PLL4, PLL_800, 434 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 435 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 436 _HSI, _HSE, _CSI, _I2S_CKIN), 437 }; 438 439 /* Prescaler table lookups for clock computation */ 440 441 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 442 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 443 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 444 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 445 0, 1, 2, 3, 4, 4, 4, 4 446 }; 447 448 /* div = /1 /2 /3 /4 */ 449 static const uint8_t stm32mp1_axi_div[8] = { 450 1, 2, 3, 4, 4, 4, 4, 4 451 }; 452 453 static const struct stm32mp1_clk_data stm32mp1_data = { 454 .gate = stm32mp1_clk_gate, 455 .sel = stm32mp1_clk_sel, 456 .pll = stm32mp1_clk_pll, 457 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), 458 }; 459 460 static struct stm32mp1_clk_priv stm32mp1_clk_priv_data; 461 462 static unsigned long stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, 463 enum stm32mp_osc_id idx) 464 { 465 if (idx >= NB_OSC) { 466 return 0; 467 } 468 469 return priv->osc[idx]; 470 } 471 472 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) 473 { 474 const struct stm32mp1_clk_gate *gate = priv->data->gate; 475 int i; 476 int nb_clks = priv->data->nb_gate; 477 478 for (i = 0; i < nb_clks; i++) { 479 if (gate[i].index == id) { 480 return i; 481 } 482 } 483 484 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 485 486 return -EINVAL; 487 } 488 489 static enum stm32mp1_parent_sel 490 stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, int i) 491 { 492 const struct stm32mp1_clk_gate *gate = priv->data->gate; 493 494 return gate[i].sel; 495 } 496 497 static enum stm32mp1_parent_id 498 stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, int i) 499 { 500 const struct stm32mp1_clk_gate *gate = priv->data->gate; 501 502 return gate[i].fixed; 503 } 504 505 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, 506 unsigned long id) 507 { 508 const struct stm32mp1_clk_sel *sel = priv->data->sel; 509 uint32_t j, p_sel; 510 int i; 511 enum stm32mp1_parent_id p; 512 enum stm32mp1_parent_sel s; 513 514 for (j = 0; j < ARRAY_SIZE(stm32mp1_clks); j++) { 515 if (stm32mp1_clks[j][0] == id) { 516 return (int)stm32mp1_clks[j][1]; 517 } 518 } 519 520 i = stm32mp1_clk_get_id(priv, id); 521 if (i < 0) { 522 return i; 523 } 524 525 p = stm32mp1_clk_get_fixed_parent(priv, i); 526 if (p < _PARENT_NB) { 527 return (int)p; 528 } 529 530 s = stm32mp1_clk_get_sel(priv, i); 531 if (s >= _PARENT_SEL_NB) { 532 return -EINVAL; 533 } 534 535 p_sel = (mmio_read_32(priv->base + sel[s].offset) >> sel[s].src) & 536 sel[s].msk; 537 538 if (p_sel < sel[s].nb_parent) { 539 return (int)sel[s].parent[p_sel]; 540 } 541 542 ERROR("%s: no parents defined for clk id %ld\n", __func__, id); 543 544 return -EINVAL; 545 } 546 547 static unsigned long stm32mp1_pll_get_fref_ck(struct stm32mp1_clk_priv *priv, 548 enum stm32mp1_pll_id pll_id) 549 { 550 const struct stm32mp1_clk_pll *pll = priv->data->pll; 551 uint32_t selr, src; 552 unsigned long refclk; 553 554 selr = mmio_read_32(priv->base + pll[pll_id].rckxselr); 555 src = selr & RCC_SELR_REFCLK_SRC_MASK; 556 557 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); 558 559 return refclk; 560 } 561 562 /* 563 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 564 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 565 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 566 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 567 */ 568 static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv, 569 enum stm32mp1_pll_id pll_id) 570 { 571 const struct stm32mp1_clk_pll *pll = priv->data->pll; 572 unsigned long refclk, fvco; 573 uint32_t cfgr1, fracr, divm, divn; 574 575 cfgr1 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr1); 576 fracr = mmio_read_32(priv->base + pll[pll_id].pllxfracr); 577 578 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 579 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 580 581 refclk = stm32mp1_pll_get_fref_ck(priv, pll_id); 582 583 /* 584 * With FRACV : 585 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 586 * Without FRACV 587 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 588 */ 589 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 590 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) 591 >> RCC_PLLNFRACR_FRACV_SHIFT; 592 unsigned long long numerator, denominator; 593 594 numerator = ((unsigned long long)divn + 1U) << 13; 595 numerator = (refclk * numerator) + fracv; 596 denominator = ((unsigned long long)divm + 1U) << 13; 597 fvco = (unsigned long)(numerator / denominator); 598 } else { 599 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 600 } 601 602 return fvco; 603 } 604 605 static unsigned long stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, 606 enum stm32mp1_pll_id pll_id, 607 enum stm32mp1_div_id div_id) 608 { 609 const struct stm32mp1_clk_pll *pll = priv->data->pll; 610 unsigned long dfout; 611 uint32_t cfgr2, divy; 612 613 if (div_id >= _DIV_NB) { 614 return 0; 615 } 616 617 cfgr2 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr2); 618 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 619 620 dfout = stm32mp1_pll_get_fvco(priv, pll_id) / (divy + 1U); 621 622 return dfout; 623 } 624 625 static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) 626 { 627 uint32_t reg, clkdiv; 628 unsigned long clock = 0; 629 630 switch (p) { 631 case _CK_MPU: 632 /* MPU sub system */ 633 reg = mmio_read_32(priv->base + RCC_MPCKSELR); 634 switch (reg & RCC_SELR_SRC_MASK) { 635 case RCC_MPCKSELR_HSI: 636 clock = stm32mp1_clk_get_fixed(priv, _HSI); 637 break; 638 case RCC_MPCKSELR_HSE: 639 clock = stm32mp1_clk_get_fixed(priv, _HSE); 640 break; 641 case RCC_MPCKSELR_PLL: 642 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 643 break; 644 case RCC_MPCKSELR_PLL_MPUDIV: 645 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 646 647 reg = mmio_read_32(priv->base + RCC_MPCKDIVR); 648 clkdiv = reg & RCC_MPUDIV_MASK; 649 if (clkdiv != 0U) { 650 clock /= stm32mp1_mpu_div[clkdiv]; 651 } 652 653 break; 654 default: 655 break; 656 } 657 break; 658 /* AXI sub system */ 659 case _ACLK: 660 case _HCLK2: 661 case _HCLK6: 662 case _PCLK4: 663 case _PCLK5: 664 reg = mmio_read_32(priv->base + RCC_ASSCKSELR); 665 switch (reg & RCC_SELR_SRC_MASK) { 666 case RCC_ASSCKSELR_HSI: 667 clock = stm32mp1_clk_get_fixed(priv, _HSI); 668 break; 669 case RCC_ASSCKSELR_HSE: 670 clock = stm32mp1_clk_get_fixed(priv, _HSE); 671 break; 672 case RCC_ASSCKSELR_PLL: 673 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 674 break; 675 default: 676 break; 677 } 678 679 /* System clock divider */ 680 reg = mmio_read_32(priv->base + RCC_AXIDIVR); 681 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 682 683 switch (p) { 684 case _PCLK4: 685 reg = mmio_read_32(priv->base + RCC_APB4DIVR); 686 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 687 break; 688 case _PCLK5: 689 reg = mmio_read_32(priv->base + RCC_APB5DIVR); 690 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 691 break; 692 default: 693 break; 694 } 695 break; 696 case _CK_PER: 697 reg = mmio_read_32(priv->base + RCC_CPERCKSELR); 698 switch (reg & RCC_SELR_SRC_MASK) { 699 case RCC_CPERCKSELR_HSI: 700 clock = stm32mp1_clk_get_fixed(priv, _HSI); 701 break; 702 case RCC_CPERCKSELR_HSE: 703 clock = stm32mp1_clk_get_fixed(priv, _HSE); 704 break; 705 case RCC_CPERCKSELR_CSI: 706 clock = stm32mp1_clk_get_fixed(priv, _CSI); 707 break; 708 default: 709 break; 710 } 711 break; 712 case _HSI: 713 case _HSI_KER: 714 clock = stm32mp1_clk_get_fixed(priv, _HSI); 715 break; 716 case _CSI: 717 case _CSI_KER: 718 clock = stm32mp1_clk_get_fixed(priv, _CSI); 719 break; 720 case _HSE: 721 case _HSE_KER: 722 clock = stm32mp1_clk_get_fixed(priv, _HSE); 723 break; 724 case _HSE_KER_DIV2: 725 clock = stm32mp1_clk_get_fixed(priv, _HSE) >> 1; 726 break; 727 case _LSI: 728 clock = stm32mp1_clk_get_fixed(priv, _LSI); 729 break; 730 case _LSE: 731 clock = stm32mp1_clk_get_fixed(priv, _LSE); 732 break; 733 /* PLL */ 734 case _PLL1_P: 735 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 736 break; 737 case _PLL1_Q: 738 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_Q); 739 break; 740 case _PLL1_R: 741 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_R); 742 break; 743 case _PLL2_P: 744 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 745 break; 746 case _PLL2_Q: 747 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_Q); 748 break; 749 case _PLL2_R: 750 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_R); 751 break; 752 case _PLL3_P: 753 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); 754 break; 755 case _PLL3_Q: 756 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_Q); 757 break; 758 case _PLL3_R: 759 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_R); 760 break; 761 case _PLL4_P: 762 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_P); 763 break; 764 case _PLL4_Q: 765 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_Q); 766 break; 767 case _PLL4_R: 768 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_R); 769 break; 770 /* Other */ 771 case _USB_PHY_48: 772 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); 773 break; 774 default: 775 break; 776 } 777 778 return clock; 779 } 780 781 bool stm32mp1_clk_is_enabled(unsigned long id) 782 { 783 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 784 const struct stm32mp1_clk_gate *gate = priv->data->gate; 785 int i = stm32mp1_clk_get_id(priv, id); 786 787 if (i < 0) { 788 return false; 789 } 790 791 return ((mmio_read_32(priv->base + gate[i].offset) & 792 BIT(gate[i].bit)) != 0U); 793 } 794 795 int stm32mp1_clk_enable(unsigned long id) 796 { 797 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 798 const struct stm32mp1_clk_gate *gate = priv->data->gate; 799 int i = stm32mp1_clk_get_id(priv, id); 800 801 if (i < 0) { 802 return i; 803 } 804 805 if (gate[i].set_clr != 0U) { 806 mmio_write_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 807 } else { 808 mmio_setbits_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 809 } 810 811 return 0; 812 } 813 814 int stm32mp1_clk_disable(unsigned long id) 815 { 816 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 817 const struct stm32mp1_clk_gate *gate = priv->data->gate; 818 int i = stm32mp1_clk_get_id(priv, id); 819 820 if (i < 0) { 821 return i; 822 } 823 824 if (gate[i].set_clr != 0U) { 825 mmio_write_32(priv->base + gate[i].offset 826 + RCC_MP_ENCLRR_OFFSET, 827 BIT(gate[i].bit)); 828 } else { 829 mmio_clrbits_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 830 } 831 832 return 0; 833 } 834 835 unsigned long stm32mp1_clk_get_rate(unsigned long id) 836 { 837 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 838 int p = stm32mp1_clk_get_parent(priv, id); 839 unsigned long rate; 840 841 if (p < 0) { 842 return 0; 843 } 844 845 rate = stm32mp1_clk_get(priv, p); 846 847 return rate; 848 } 849 850 static void stm32mp1_ls_osc_set(int enable, uint32_t rcc, uint32_t offset, 851 uint32_t mask_on) 852 { 853 uint32_t address = rcc + offset; 854 855 if (enable != 0) { 856 mmio_setbits_32(address, mask_on); 857 } else { 858 mmio_clrbits_32(address, mask_on); 859 } 860 } 861 862 static void stm32mp1_hs_ocs_set(int enable, uint32_t rcc, uint32_t mask_on) 863 { 864 if (enable != 0) { 865 mmio_setbits_32(rcc + RCC_OCENSETR, mask_on); 866 } else { 867 mmio_setbits_32(rcc + RCC_OCENCLRR, mask_on); 868 } 869 } 870 871 static int stm32mp1_osc_wait(int enable, uint32_t rcc, uint32_t offset, 872 uint32_t mask_rdy) 873 { 874 unsigned long start; 875 uint32_t mask_test; 876 uint32_t address = rcc + offset; 877 878 if (enable != 0) { 879 mask_test = mask_rdy; 880 } else { 881 mask_test = 0; 882 } 883 884 start = get_timer(0); 885 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 886 if (get_timer(start) > OSCRDY_TIMEOUT) { 887 ERROR("OSC %x @ %x timeout for enable=%d : 0x%x\n", 888 mask_rdy, address, enable, mmio_read_32(address)); 889 return -ETIMEDOUT; 890 } 891 } 892 893 return 0; 894 } 895 896 static void stm32mp1_lse_enable(uint32_t rcc, bool bypass, uint32_t lsedrv) 897 { 898 uint32_t value; 899 900 if (bypass) { 901 mmio_setbits_32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); 902 } 903 904 /* 905 * Warning: not recommended to switch directly from "high drive" 906 * to "medium low drive", and vice-versa. 907 */ 908 value = (mmio_read_32(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 909 RCC_BDCR_LSEDRV_SHIFT; 910 911 while (value != lsedrv) { 912 if (value > lsedrv) { 913 value--; 914 } else { 915 value++; 916 } 917 918 mmio_clrsetbits_32(rcc + RCC_BDCR, 919 RCC_BDCR_LSEDRV_MASK, 920 value << RCC_BDCR_LSEDRV_SHIFT); 921 } 922 923 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); 924 } 925 926 static void stm32mp1_lse_wait(uint32_t rcc) 927 { 928 if (stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 929 VERBOSE("%s: failed\n", __func__); 930 } 931 } 932 933 static void stm32mp1_lsi_set(uint32_t rcc, int enable) 934 { 935 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); 936 if (stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 937 0) { 938 VERBOSE("%s: failed\n", __func__); 939 } 940 } 941 942 static void stm32mp1_hse_enable(uint32_t rcc, bool bypass, bool css) 943 { 944 if (bypass) { 945 mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP); 946 } 947 948 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); 949 if (stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 950 0) { 951 VERBOSE("%s: failed\n", __func__); 952 } 953 954 if (css) { 955 mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); 956 } 957 } 958 959 static void stm32mp1_csi_set(uint32_t rcc, int enable) 960 { 961 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); 962 if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 963 0) { 964 VERBOSE("%s: failed\n", __func__); 965 } 966 } 967 968 static void stm32mp1_hsi_set(uint32_t rcc, int enable) 969 { 970 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); 971 if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 972 0) { 973 VERBOSE("%s: failed\n", __func__); 974 } 975 } 976 977 static int stm32mp1_set_hsidiv(uint32_t rcc, uint8_t hsidiv) 978 { 979 unsigned long start; 980 uint32_t address = rcc + RCC_OCRDYR; 981 982 mmio_clrsetbits_32(rcc + RCC_HSICFGR, 983 RCC_HSICFGR_HSIDIV_MASK, 984 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 985 986 start = get_timer(0); 987 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 988 if (get_timer(start) > HSIDIV_TIMEOUT) { 989 ERROR("HSIDIV failed @ 0x%x: 0x%x\n", 990 address, mmio_read_32(address)); 991 return -ETIMEDOUT; 992 } 993 } 994 995 return 0; 996 } 997 998 static int stm32mp1_hsidiv(uint32_t rcc, unsigned long hsifreq) 999 { 1000 uint8_t hsidiv; 1001 uint32_t hsidivfreq = MAX_HSI_HZ; 1002 1003 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1004 if (hsidivfreq == hsifreq) { 1005 break; 1006 } 1007 1008 hsidivfreq /= 2U; 1009 } 1010 1011 if (hsidiv == 4U) { 1012 ERROR("Invalid clk-hsi frequency\n"); 1013 return -1; 1014 } 1015 1016 if (hsidiv != 0U) { 1017 return stm32mp1_set_hsidiv(rcc, hsidiv); 1018 } 1019 1020 return 0; 1021 } 1022 1023 static void stm32mp1_pll_start(struct stm32mp1_clk_priv *priv, 1024 enum stm32mp1_pll_id pll_id) 1025 { 1026 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1027 1028 mmio_write_32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_PLLON); 1029 } 1030 1031 static int stm32mp1_pll_output(struct stm32mp1_clk_priv *priv, 1032 enum stm32mp1_pll_id pll_id, uint32_t output) 1033 { 1034 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1035 uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; 1036 unsigned long start; 1037 1038 start = get_timer(0); 1039 /* Wait PLL lock */ 1040 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1041 if (get_timer(start) > PLLRDY_TIMEOUT) { 1042 ERROR("PLL%d start failed @ 0x%x: 0x%x\n", 1043 pll_id, pllxcr, mmio_read_32(pllxcr)); 1044 return -ETIMEDOUT; 1045 } 1046 } 1047 1048 /* Start the requested output */ 1049 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1050 1051 return 0; 1052 } 1053 1054 static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv, 1055 enum stm32mp1_pll_id pll_id) 1056 { 1057 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1058 uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; 1059 unsigned long start; 1060 1061 /* Stop all output */ 1062 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1063 RCC_PLLNCR_DIVREN); 1064 1065 /* Stop PLL */ 1066 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1067 1068 start = get_timer(0); 1069 /* Wait PLL stopped */ 1070 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1071 if (get_timer(start) > PLLRDY_TIMEOUT) { 1072 ERROR("PLL%d stop failed @ 0x%x: 0x%x\n", 1073 pll_id, pllxcr, mmio_read_32(pllxcr)); 1074 return -ETIMEDOUT; 1075 } 1076 } 1077 1078 return 0; 1079 } 1080 1081 static void stm32mp1_pll_config_output(struct stm32mp1_clk_priv *priv, 1082 enum stm32mp1_pll_id pll_id, 1083 uint32_t *pllcfg) 1084 { 1085 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1086 uint32_t rcc = priv->base; 1087 uint32_t value; 1088 1089 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1090 RCC_PLLNCFGR2_DIVP_MASK; 1091 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1092 RCC_PLLNCFGR2_DIVQ_MASK; 1093 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1094 RCC_PLLNCFGR2_DIVR_MASK; 1095 mmio_write_32(rcc + pll[pll_id].pllxcfgr2, value); 1096 } 1097 1098 static int stm32mp1_pll_config(struct stm32mp1_clk_priv *priv, 1099 enum stm32mp1_pll_id pll_id, 1100 uint32_t *pllcfg, uint32_t fracv) 1101 { 1102 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1103 uint32_t rcc = priv->base; 1104 enum stm32mp1_plltype type = pll[pll_id].plltype; 1105 unsigned long refclk; 1106 uint32_t ifrge = 0; 1107 uint32_t src, value; 1108 1109 src = mmio_read_32(priv->base + pll[pll_id].rckxselr) & 1110 RCC_SELR_REFCLK_SRC_MASK; 1111 1112 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / 1113 (pllcfg[PLLCFG_M] + 1U); 1114 1115 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1116 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1117 return -EINVAL; 1118 } 1119 1120 if ((type == PLL_800) && (refclk >= 8000000U)) { 1121 ifrge = 1U; 1122 } 1123 1124 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1125 RCC_PLLNCFGR1_DIVN_MASK; 1126 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1127 RCC_PLLNCFGR1_DIVM_MASK; 1128 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1129 RCC_PLLNCFGR1_IFRGE_MASK; 1130 mmio_write_32(rcc + pll[pll_id].pllxcfgr1, value); 1131 1132 /* Fractional configuration */ 1133 value = 0; 1134 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1135 1136 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1137 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1138 1139 value |= RCC_PLLNFRACR_FRACLE; 1140 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1141 1142 stm32mp1_pll_config_output(priv, pll_id, pllcfg); 1143 1144 return 0; 1145 } 1146 1147 static void stm32mp1_pll_csg(struct stm32mp1_clk_priv *priv, 1148 enum stm32mp1_pll_id pll_id, 1149 uint32_t *csg) 1150 { 1151 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1152 uint32_t pllxcsg = 0; 1153 1154 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1155 RCC_PLLNCSGR_MOD_PER_MASK; 1156 1157 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1158 RCC_PLLNCSGR_INC_STEP_MASK; 1159 1160 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1161 RCC_PLLNCSGR_SSCG_MODE_MASK; 1162 1163 mmio_write_32(priv->base + pll[pll_id].pllxcsgr, pllxcsg); 1164 } 1165 1166 static int stm32mp1_set_clksrc(struct stm32mp1_clk_priv *priv, 1167 unsigned int clksrc) 1168 { 1169 uint32_t address = priv->base + (clksrc >> 4); 1170 unsigned long start; 1171 1172 mmio_clrsetbits_32(address, RCC_SELR_SRC_MASK, 1173 clksrc & RCC_SELR_SRC_MASK); 1174 1175 start = get_timer(0); 1176 while ((mmio_read_32(address) & RCC_SELR_SRCRDY) == 0U) { 1177 if (get_timer(start) > CLKSRC_TIMEOUT) { 1178 ERROR("CLKSRC %x start failed @ 0x%x: 0x%x\n", 1179 clksrc, address, mmio_read_32(address)); 1180 return -ETIMEDOUT; 1181 } 1182 } 1183 1184 return 0; 1185 } 1186 1187 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uint32_t address) 1188 { 1189 unsigned long start; 1190 1191 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1192 clkdiv & RCC_DIVR_DIV_MASK); 1193 1194 start = get_timer(0); 1195 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1196 if (get_timer(start) > CLKDIV_TIMEOUT) { 1197 ERROR("CLKDIV %x start failed @ 0x%x: 0x%x\n", 1198 clkdiv, address, mmio_read_32(address)); 1199 return -ETIMEDOUT; 1200 } 1201 } 1202 1203 return 0; 1204 } 1205 1206 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, 1207 uint32_t clksrc, uint32_t clkdiv) 1208 { 1209 uint32_t address = priv->base + (clksrc >> 4); 1210 1211 /* 1212 * Binding clksrc : 1213 * bit15-4 offset 1214 * bit3: disable 1215 * bit2-0: MCOSEL[2:0] 1216 */ 1217 if ((clksrc & 0x8U) != 0U) { 1218 mmio_clrbits_32(address, RCC_MCOCFG_MCOON); 1219 } else { 1220 mmio_clrsetbits_32(address, 1221 RCC_MCOCFG_MCOSRC_MASK, 1222 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1223 mmio_clrsetbits_32(address, 1224 RCC_MCOCFG_MCODIV_MASK, 1225 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1226 mmio_setbits_32(address, RCC_MCOCFG_MCOON); 1227 } 1228 } 1229 1230 static void stm32mp1_set_rtcsrc(struct stm32mp1_clk_priv *priv, 1231 unsigned int clksrc, bool lse_css) 1232 { 1233 uint32_t address = priv->base + RCC_BDCR; 1234 1235 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1236 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1237 mmio_clrsetbits_32(address, 1238 RCC_BDCR_RTCSRC_MASK, 1239 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1240 1241 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1242 } 1243 1244 if (lse_css) { 1245 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1246 } 1247 } 1248 1249 #define CNTCVL_OFF 0x008 1250 #define CNTCVU_OFF 0x00C 1251 1252 static void stm32mp1_stgen_config(struct stm32mp1_clk_priv *priv) 1253 { 1254 uintptr_t stgen; 1255 int p; 1256 uint32_t cntfid0; 1257 unsigned long rate; 1258 1259 stgen = fdt_get_stgen_base(); 1260 1261 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1262 p = stm32mp1_clk_get_parent(priv, STGEN_K); 1263 rate = stm32mp1_clk_get(priv, p); 1264 1265 if (cntfid0 != rate) { 1266 unsigned long long counter; 1267 1268 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1269 counter = (unsigned long long) 1270 mmio_read_32(stgen + CNTCVL_OFF); 1271 counter |= ((unsigned long long) 1272 (mmio_read_32(stgen + CNTCVU_OFF))) << 32; 1273 counter = (counter * rate / cntfid0); 1274 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1275 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1276 mmio_write_32(stgen + CNTFID_OFF, rate); 1277 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1278 1279 write_cntfrq((u_register_t)rate); 1280 1281 /* Need to update timer with new frequency */ 1282 generic_delay_timer_init(); 1283 } 1284 } 1285 1286 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1287 { 1288 uintptr_t stgen; 1289 unsigned long long cnt; 1290 1291 stgen = fdt_get_stgen_base(); 1292 1293 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1294 mmio_read_32(stgen + CNTCVL_OFF); 1295 1296 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1297 1298 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1299 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1300 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1301 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1302 } 1303 1304 static void stm32mp1_pkcs_config(struct stm32mp1_clk_priv *priv, uint32_t pkcs) 1305 { 1306 uint32_t address = priv->base + ((pkcs >> 4) & 0xFFFU); 1307 uint32_t value = pkcs & 0xFU; 1308 uint32_t mask = 0xFU; 1309 1310 if ((pkcs & BIT(31)) != 0U) { 1311 mask <<= 4; 1312 value <<= 4; 1313 } 1314 1315 mmio_clrsetbits_32(address, mask, value); 1316 } 1317 1318 int stm32mp1_clk_init(void) 1319 { 1320 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1321 uint32_t rcc = priv->base; 1322 unsigned int clksrc[CLKSRC_NB]; 1323 unsigned int clkdiv[CLKDIV_NB]; 1324 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1325 int plloff[_PLL_NB]; 1326 int ret, len; 1327 enum stm32mp1_pll_id i; 1328 bool lse_css = false; 1329 const fdt32_t *pkcs_cell; 1330 1331 /* Check status field to disable security */ 1332 if (!fdt_get_rcc_secure_status()) { 1333 mmio_write_32(rcc + RCC_TZCR, 0); 1334 } 1335 1336 ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc, 1337 (uint32_t)CLKSRC_NB); 1338 if (ret < 0) { 1339 return -FDT_ERR_NOTFOUND; 1340 } 1341 1342 ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv, 1343 (uint32_t)CLKDIV_NB); 1344 if (ret < 0) { 1345 return -FDT_ERR_NOTFOUND; 1346 } 1347 1348 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1349 char name[12]; 1350 1351 snprintf(name, sizeof(name), "st,pll@%d", i); 1352 plloff[i] = fdt_rcc_subnode_offset(name); 1353 1354 if (!fdt_check_node(plloff[i])) { 1355 continue; 1356 } 1357 1358 ret = fdt_read_uint32_array(plloff[i], "cfg", 1359 pllcfg[i], (int)PLLCFG_NB); 1360 if (ret < 0) { 1361 return -FDT_ERR_NOTFOUND; 1362 } 1363 } 1364 1365 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1366 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1367 1368 /* 1369 * Switch ON oscillator found in device-tree. 1370 * Note: HSI already ON after BootROM stage. 1371 */ 1372 if (priv->osc[_LSI] != 0U) { 1373 stm32mp1_lsi_set(rcc, 1); 1374 } 1375 if (priv->osc[_LSE] != 0U) { 1376 bool bypass; 1377 uint32_t lsedrv; 1378 1379 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1380 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1381 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1382 LSEDRV_MEDIUM_HIGH); 1383 stm32mp1_lse_enable(rcc, bypass, lsedrv); 1384 } 1385 if (priv->osc[_HSE] != 0U) { 1386 bool bypass, css; 1387 1388 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1389 css = fdt_osc_read_bool(_LSE, "st,css"); 1390 stm32mp1_hse_enable(rcc, bypass, css); 1391 } 1392 /* 1393 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1394 * => switch on CSI even if node is not present in device tree 1395 */ 1396 stm32mp1_csi_set(rcc, 1); 1397 1398 /* Come back to HSI */ 1399 ret = stm32mp1_set_clksrc(priv, CLK_MPU_HSI); 1400 if (ret != 0) { 1401 return ret; 1402 } 1403 ret = stm32mp1_set_clksrc(priv, CLK_AXI_HSI); 1404 if (ret != 0) { 1405 return ret; 1406 } 1407 1408 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1409 if (i == _PLL4) 1410 continue; 1411 ret = stm32mp1_pll_stop(priv, i); 1412 if (ret != 0) { 1413 return ret; 1414 } 1415 } 1416 1417 /* Configure HSIDIV */ 1418 if (priv->osc[_HSI] != 0U) { 1419 ret = stm32mp1_hsidiv(rcc, priv->osc[_HSI]); 1420 if (ret != 0) { 1421 return ret; 1422 } 1423 stm32mp1_stgen_config(priv); 1424 } 1425 1426 /* Select DIV */ 1427 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1428 mmio_write_32(rcc + RCC_MPCKDIVR, 1429 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1430 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); 1431 if (ret != 0) { 1432 return ret; 1433 } 1434 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); 1435 if (ret != 0) { 1436 return ret; 1437 } 1438 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); 1439 if (ret != 0) { 1440 return ret; 1441 } 1442 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); 1443 if (ret != 0) { 1444 return ret; 1445 } 1446 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); 1447 if (ret != 0) { 1448 return ret; 1449 } 1450 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); 1451 if (ret != 0) { 1452 return ret; 1453 } 1454 1455 /* No ready bit for RTC */ 1456 mmio_write_32(rcc + RCC_RTCDIVR, 1457 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1458 1459 /* Configure PLLs source */ 1460 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL12]); 1461 if (ret != 0) { 1462 return ret; 1463 } 1464 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL3]); 1465 if (ret != 0) { 1466 return ret; 1467 } 1468 1469 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL4]); 1470 if (ret != 0) { 1471 return ret; 1472 } 1473 1474 /* Configure and start PLLs */ 1475 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1476 uint32_t fracv; 1477 uint32_t csg[PLLCSG_NB]; 1478 1479 if (!fdt_check_node(plloff[i])) { 1480 continue; 1481 } 1482 1483 fracv = fdt_read_uint32_default(plloff[i], "frac", 0); 1484 1485 ret = stm32mp1_pll_config(priv, i, pllcfg[i], fracv); 1486 if (ret != 0) { 1487 return ret; 1488 } 1489 ret = fdt_read_uint32_array(plloff[i], "csg", csg, 1490 (uint32_t)PLLCSG_NB); 1491 if (ret == 0) { 1492 stm32mp1_pll_csg(priv, i, csg); 1493 } else if (ret != -FDT_ERR_NOTFOUND) { 1494 return ret; 1495 } 1496 1497 stm32mp1_pll_start(priv, i); 1498 } 1499 /* Wait and start PLLs ouptut when ready */ 1500 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1501 if (!fdt_check_node(plloff[i])) { 1502 continue; 1503 } 1504 1505 ret = stm32mp1_pll_output(priv, i, pllcfg[i][PLLCFG_O]); 1506 if (ret != 0) { 1507 return ret; 1508 } 1509 } 1510 /* Wait LSE ready before to use it */ 1511 if (priv->osc[_LSE] != 0U) { 1512 stm32mp1_lse_wait(rcc); 1513 } 1514 1515 /* Configure with expected clock source */ 1516 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_MPU]); 1517 if (ret != 0) { 1518 return ret; 1519 } 1520 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_AXI]); 1521 if (ret != 0) { 1522 return ret; 1523 } 1524 stm32mp1_set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); 1525 1526 /* Configure PKCK */ 1527 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1528 if (pkcs_cell != NULL) { 1529 bool ckper_disabled = false; 1530 uint32_t j; 1531 1532 priv->pkcs_usb_value = 0; 1533 1534 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1535 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1536 1537 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1538 ckper_disabled = true; 1539 continue; 1540 } 1541 stm32mp1_pkcs_config(priv, pkcs); 1542 } 1543 1544 /* 1545 * CKPER is source for some peripheral clocks 1546 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1547 * only if previous clock is still ON 1548 * => deactivated CKPER only after switching clock 1549 */ 1550 if (ckper_disabled) { 1551 stm32mp1_pkcs_config(priv, CLK_CKPER_DISABLED); 1552 } 1553 } 1554 1555 /* Switch OFF HSI if not found in device-tree */ 1556 if (priv->osc[_HSI] == 0U) { 1557 stm32mp1_hsi_set(rcc, 0); 1558 } 1559 stm32mp1_stgen_config(priv); 1560 1561 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1562 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, 1563 RCC_DDRITFCR_DDRCKMOD_MASK, 1564 RCC_DDRITFCR_DDRCKMOD_SSR << 1565 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1566 1567 return 0; 1568 } 1569 1570 static void stm32mp1_osc_clk_init(const char *name, 1571 struct stm32mp1_clk_priv *priv, 1572 enum stm32mp_osc_id index) 1573 { 1574 uint32_t frequency; 1575 1576 priv->osc[index] = 0; 1577 1578 if (fdt_osc_read_freq(name, &frequency) != 0) { 1579 ERROR("%s frequency request failed\n", name); 1580 panic(); 1581 } else { 1582 priv->osc[index] = frequency; 1583 } 1584 } 1585 1586 static void stm32mp1_osc_init(void) 1587 { 1588 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1589 enum stm32mp_osc_id i; 1590 1591 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 1592 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], priv, i); 1593 } 1594 } 1595 1596 int stm32mp1_clk_probe(void) 1597 { 1598 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1599 1600 priv->base = fdt_rcc_read_addr(); 1601 if (priv->base == 0U) { 1602 return -EINVAL; 1603 } 1604 1605 priv->data = &stm32mp1_data; 1606 1607 if ((priv->data->gate == NULL) || (priv->data->sel == NULL) || 1608 (priv->data->pll == NULL)) { 1609 return -EINVAL; 1610 } 1611 1612 stm32mp1_osc_init(); 1613 1614 return 0; 1615 } 1616