1 /* 2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <common/fdt_wrappers.h> 20 #include <drivers/delay_timer.h> 21 #include <drivers/generic_delay_timer.h> 22 #include <drivers/st/stm32mp_clkfunc.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_rcc.h> 25 #include <dt-bindings/clock/stm32mp1-clksrc.h> 26 #include <lib/mmio.h> 27 #include <lib/spinlock.h> 28 #include <lib/utils_def.h> 29 #include <plat/common/platform.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _CSI_KER, 60 _PLL1_P, 61 _PLL1_Q, 62 _PLL1_R, 63 _PLL2_P, 64 _PLL2_Q, 65 _PLL2_R, 66 _PLL3_P, 67 _PLL3_Q, 68 _PLL3_R, 69 _PLL4_P, 70 _PLL4_Q, 71 _PLL4_R, 72 _ACLK, 73 _PCLK1, 74 _PCLK2, 75 _PCLK3, 76 _PCLK4, 77 _PCLK5, 78 _HCLK6, 79 _HCLK2, 80 _CK_PER, 81 _CK_MPU, 82 _CK_MCU, 83 _USB_PHY_48, 84 _PARENT_NB, 85 _UNKNOWN_ID = 0xff, 86 }; 87 88 /* Lists only the parent clock we are interested in */ 89 enum stm32mp1_parent_sel { 90 _I2C12_SEL, 91 _I2C35_SEL, 92 _STGEN_SEL, 93 _I2C46_SEL, 94 _SPI6_SEL, 95 _UART1_SEL, 96 _RNG1_SEL, 97 _UART6_SEL, 98 _UART24_SEL, 99 _UART35_SEL, 100 _UART78_SEL, 101 _SDMMC12_SEL, 102 _SDMMC3_SEL, 103 _QSPI_SEL, 104 _FMC_SEL, 105 _AXIS_SEL, 106 _MCUS_SEL, 107 _USBPHY_SEL, 108 _USBO_SEL, 109 _MPU_SEL, 110 _PER_SEL, 111 _RTC_SEL, 112 _PARENT_SEL_NB, 113 _UNKNOWN_SEL = 0xff, 114 }; 115 116 /* State the parent clock ID straight related to a clock */ 117 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 118 [_HSE] = CK_HSE, 119 [_HSI] = CK_HSI, 120 [_CSI] = CK_CSI, 121 [_LSE] = CK_LSE, 122 [_LSI] = CK_LSI, 123 [_I2S_CKIN] = _UNKNOWN_ID, 124 [_USB_PHY_48] = _UNKNOWN_ID, 125 [_HSI_KER] = CK_HSI, 126 [_HSE_KER] = CK_HSE, 127 [_HSE_KER_DIV2] = CK_HSE_DIV2, 128 [_CSI_KER] = CK_CSI, 129 [_PLL1_P] = PLL1_P, 130 [_PLL1_Q] = PLL1_Q, 131 [_PLL1_R] = PLL1_R, 132 [_PLL2_P] = PLL2_P, 133 [_PLL2_Q] = PLL2_Q, 134 [_PLL2_R] = PLL2_R, 135 [_PLL3_P] = PLL3_P, 136 [_PLL3_Q] = PLL3_Q, 137 [_PLL3_R] = PLL3_R, 138 [_PLL4_P] = PLL4_P, 139 [_PLL4_Q] = PLL4_Q, 140 [_PLL4_R] = PLL4_R, 141 [_ACLK] = CK_AXI, 142 [_PCLK1] = CK_AXI, 143 [_PCLK2] = CK_AXI, 144 [_PCLK3] = CK_AXI, 145 [_PCLK4] = CK_AXI, 146 [_PCLK5] = CK_AXI, 147 [_CK_PER] = CK_PER, 148 [_CK_MPU] = CK_MPU, 149 [_CK_MCU] = CK_MCU, 150 }; 151 152 static unsigned int clock_id2parent_id(unsigned long id) 153 { 154 unsigned int n; 155 156 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 157 if (parent_id_clock_id[n] == id) { 158 return n; 159 } 160 } 161 162 return _UNKNOWN_ID; 163 } 164 165 enum stm32mp1_pll_id { 166 _PLL1, 167 _PLL2, 168 _PLL3, 169 _PLL4, 170 _PLL_NB 171 }; 172 173 enum stm32mp1_div_id { 174 _DIV_P, 175 _DIV_Q, 176 _DIV_R, 177 _DIV_NB, 178 }; 179 180 enum stm32mp1_clksrc_id { 181 CLKSRC_MPU, 182 CLKSRC_AXI, 183 CLKSRC_MCU, 184 CLKSRC_PLL12, 185 CLKSRC_PLL3, 186 CLKSRC_PLL4, 187 CLKSRC_RTC, 188 CLKSRC_MCO1, 189 CLKSRC_MCO2, 190 CLKSRC_NB 191 }; 192 193 enum stm32mp1_clkdiv_id { 194 CLKDIV_MPU, 195 CLKDIV_AXI, 196 CLKDIV_MCU, 197 CLKDIV_APB1, 198 CLKDIV_APB2, 199 CLKDIV_APB3, 200 CLKDIV_APB4, 201 CLKDIV_APB5, 202 CLKDIV_RTC, 203 CLKDIV_MCO1, 204 CLKDIV_MCO2, 205 CLKDIV_NB 206 }; 207 208 enum stm32mp1_pllcfg { 209 PLLCFG_M, 210 PLLCFG_N, 211 PLLCFG_P, 212 PLLCFG_Q, 213 PLLCFG_R, 214 PLLCFG_O, 215 PLLCFG_NB 216 }; 217 218 enum stm32mp1_pllcsg { 219 PLLCSG_MOD_PER, 220 PLLCSG_INC_STEP, 221 PLLCSG_SSCG_MODE, 222 PLLCSG_NB 223 }; 224 225 enum stm32mp1_plltype { 226 PLL_800, 227 PLL_1600, 228 PLL_TYPE_NB 229 }; 230 231 struct stm32mp1_pll { 232 uint8_t refclk_min; 233 uint8_t refclk_max; 234 uint8_t divn_max; 235 }; 236 237 struct stm32mp1_clk_gate { 238 uint16_t offset; 239 uint8_t bit; 240 uint8_t index; 241 uint8_t set_clr; 242 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 243 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 244 }; 245 246 struct stm32mp1_clk_sel { 247 uint16_t offset; 248 uint8_t src; 249 uint8_t msk; 250 uint8_t nb_parent; 251 const uint8_t *parent; 252 }; 253 254 #define REFCLK_SIZE 4 255 struct stm32mp1_clk_pll { 256 enum stm32mp1_plltype plltype; 257 uint16_t rckxselr; 258 uint16_t pllxcfgr1; 259 uint16_t pllxcfgr2; 260 uint16_t pllxfracr; 261 uint16_t pllxcr; 262 uint16_t pllxcsgr; 263 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 264 }; 265 266 /* Clocks with selectable source and non set/clr register access */ 267 #define _CLK_SELEC(off, b, idx, s) \ 268 { \ 269 .offset = (off), \ 270 .bit = (b), \ 271 .index = (idx), \ 272 .set_clr = 0, \ 273 .sel = (s), \ 274 .fixed = _UNKNOWN_ID, \ 275 } 276 277 /* Clocks with fixed source and non set/clr register access */ 278 #define _CLK_FIXED(off, b, idx, f) \ 279 { \ 280 .offset = (off), \ 281 .bit = (b), \ 282 .index = (idx), \ 283 .set_clr = 0, \ 284 .sel = _UNKNOWN_SEL, \ 285 .fixed = (f), \ 286 } 287 288 /* Clocks with selectable source and set/clr register access */ 289 #define _CLK_SC_SELEC(off, b, idx, s) \ 290 { \ 291 .offset = (off), \ 292 .bit = (b), \ 293 .index = (idx), \ 294 .set_clr = 1, \ 295 .sel = (s), \ 296 .fixed = _UNKNOWN_ID, \ 297 } 298 299 /* Clocks with fixed source and set/clr register access */ 300 #define _CLK_SC_FIXED(off, b, idx, f) \ 301 { \ 302 .offset = (off), \ 303 .bit = (b), \ 304 .index = (idx), \ 305 .set_clr = 1, \ 306 .sel = _UNKNOWN_SEL, \ 307 .fixed = (f), \ 308 } 309 310 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 311 [_ ## _label ## _SEL] = { \ 312 .offset = _rcc_selr, \ 313 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 314 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 315 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 316 .parent = (_parents), \ 317 .nb_parent = ARRAY_SIZE(_parents) \ 318 } 319 320 #define _CLK_PLL(idx, type, off1, off2, off3, \ 321 off4, off5, off6, \ 322 p1, p2, p3, p4) \ 323 [(idx)] = { \ 324 .plltype = (type), \ 325 .rckxselr = (off1), \ 326 .pllxcfgr1 = (off2), \ 327 .pllxcfgr2 = (off3), \ 328 .pllxfracr = (off4), \ 329 .pllxcr = (off5), \ 330 .pllxcsgr = (off6), \ 331 .refclk[0] = (p1), \ 332 .refclk[1] = (p2), \ 333 .refclk[2] = (p3), \ 334 .refclk[3] = (p4), \ 335 } 336 337 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 338 339 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 340 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 341 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 342 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 343 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 344 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 345 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 346 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 347 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 348 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 349 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 350 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 351 352 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 353 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 354 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 355 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 356 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 357 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 358 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 359 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 360 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 361 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 362 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 363 364 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 365 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 366 367 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 368 369 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 370 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 371 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 372 373 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 374 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 375 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 376 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 377 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 378 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 379 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 380 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 381 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 382 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 383 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 384 385 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 386 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 387 388 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 389 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 390 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 391 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 392 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 393 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 394 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 395 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 396 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 397 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 398 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 399 400 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 401 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 402 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 403 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 404 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 405 406 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 407 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 408 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 409 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 410 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 411 412 _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL), 413 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 414 }; 415 416 static const uint8_t i2c12_parents[] = { 417 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 418 }; 419 420 static const uint8_t i2c35_parents[] = { 421 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 422 }; 423 424 static const uint8_t stgen_parents[] = { 425 _HSI_KER, _HSE_KER 426 }; 427 428 static const uint8_t i2c46_parents[] = { 429 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 430 }; 431 432 static const uint8_t spi6_parents[] = { 433 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 434 }; 435 436 static const uint8_t usart1_parents[] = { 437 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 438 }; 439 440 static const uint8_t rng1_parents[] = { 441 _CSI, _PLL4_R, _LSE, _LSI 442 }; 443 444 static const uint8_t uart6_parents[] = { 445 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 446 }; 447 448 static const uint8_t uart234578_parents[] = { 449 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 450 }; 451 452 static const uint8_t sdmmc12_parents[] = { 453 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 454 }; 455 456 static const uint8_t sdmmc3_parents[] = { 457 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 458 }; 459 460 static const uint8_t qspi_parents[] = { 461 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 462 }; 463 464 static const uint8_t fmc_parents[] = { 465 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 466 }; 467 468 static const uint8_t ass_parents[] = { 469 _HSI, _HSE, _PLL2 470 }; 471 472 static const uint8_t mss_parents[] = { 473 _HSI, _HSE, _CSI, _PLL3 474 }; 475 476 static const uint8_t usbphy_parents[] = { 477 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 478 }; 479 480 static const uint8_t usbo_parents[] = { 481 _PLL4_R, _USB_PHY_48 482 }; 483 484 static const uint8_t mpu_parents[] = { 485 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 486 }; 487 488 static const uint8_t per_parents[] = { 489 _HSI, _HSE, _CSI, 490 }; 491 492 static const uint8_t rtc_parents[] = { 493 _UNKNOWN_ID, _LSE, _LSI, _HSE 494 }; 495 496 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 497 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 498 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 499 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 500 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 501 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 502 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 503 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 504 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 505 _CLK_PARENT_SEL(PER, RCC_CPERCKSELR, per_parents), 506 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 507 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 508 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 509 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 510 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 511 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 512 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 513 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 514 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 515 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents), 516 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents), 517 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 518 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 519 }; 520 521 /* Define characteristic of PLL according type */ 522 #define DIVN_MIN 24 523 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 524 [PLL_800] = { 525 .refclk_min = 4, 526 .refclk_max = 16, 527 .divn_max = 99, 528 }, 529 [PLL_1600] = { 530 .refclk_min = 8, 531 .refclk_max = 16, 532 .divn_max = 199, 533 }, 534 }; 535 536 /* PLLNCFGR2 register divider by output */ 537 static const uint8_t pllncfgr2[_DIV_NB] = { 538 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 539 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 540 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 541 }; 542 543 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 544 _CLK_PLL(_PLL1, PLL_1600, 545 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 546 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 547 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 548 _CLK_PLL(_PLL2, PLL_1600, 549 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 550 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 551 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 552 _CLK_PLL(_PLL3, PLL_800, 553 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 554 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 555 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 556 _CLK_PLL(_PLL4, PLL_800, 557 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 558 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 559 _HSI, _HSE, _CSI, _I2S_CKIN), 560 }; 561 562 /* Prescaler table lookups for clock computation */ 563 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 564 static const uint8_t stm32mp1_mcu_div[16] = { 565 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 566 }; 567 568 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 569 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 570 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 571 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 572 0, 1, 2, 3, 4, 4, 4, 4 573 }; 574 575 /* div = /1 /2 /3 /4 */ 576 static const uint8_t stm32mp1_axi_div[8] = { 577 1, 2, 3, 4, 4, 4, 4, 4 578 }; 579 580 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 581 [_HSI] = "HSI", 582 [_HSE] = "HSE", 583 [_CSI] = "CSI", 584 [_LSI] = "LSI", 585 [_LSE] = "LSE", 586 [_I2S_CKIN] = "I2S_CKIN", 587 [_HSI_KER] = "HSI_KER", 588 [_HSE_KER] = "HSE_KER", 589 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 590 [_CSI_KER] = "CSI_KER", 591 [_PLL1_P] = "PLL1_P", 592 [_PLL1_Q] = "PLL1_Q", 593 [_PLL1_R] = "PLL1_R", 594 [_PLL2_P] = "PLL2_P", 595 [_PLL2_Q] = "PLL2_Q", 596 [_PLL2_R] = "PLL2_R", 597 [_PLL3_P] = "PLL3_P", 598 [_PLL3_Q] = "PLL3_Q", 599 [_PLL3_R] = "PLL3_R", 600 [_PLL4_P] = "PLL4_P", 601 [_PLL4_Q] = "PLL4_Q", 602 [_PLL4_R] = "PLL4_R", 603 [_ACLK] = "ACLK", 604 [_PCLK1] = "PCLK1", 605 [_PCLK2] = "PCLK2", 606 [_PCLK3] = "PCLK3", 607 [_PCLK4] = "PCLK4", 608 [_PCLK5] = "PCLK5", 609 [_HCLK6] = "KCLK6", 610 [_HCLK2] = "HCLK2", 611 [_CK_PER] = "CK_PER", 612 [_CK_MPU] = "CK_MPU", 613 [_CK_MCU] = "CK_MCU", 614 [_USB_PHY_48] = "USB_PHY_48", 615 }; 616 617 /* RCC clock device driver private */ 618 static unsigned long stm32mp1_osc[NB_OSC]; 619 static struct spinlock reg_lock; 620 static unsigned int gate_refcounts[NB_GATES]; 621 static struct spinlock refcount_lock; 622 623 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 624 { 625 return &stm32mp1_clk_gate[idx]; 626 } 627 628 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 629 { 630 return &stm32mp1_clk_sel[idx]; 631 } 632 633 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 634 { 635 return &stm32mp1_clk_pll[idx]; 636 } 637 638 static void stm32mp1_clk_lock(struct spinlock *lock) 639 { 640 if (stm32mp_lock_available()) { 641 /* Assume interrupts are masked */ 642 spin_lock(lock); 643 } 644 } 645 646 static void stm32mp1_clk_unlock(struct spinlock *lock) 647 { 648 if (stm32mp_lock_available()) { 649 spin_unlock(lock); 650 } 651 } 652 653 bool stm32mp1_rcc_is_secure(void) 654 { 655 uintptr_t rcc_base = stm32mp_rcc_base(); 656 657 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0; 658 } 659 660 bool stm32mp1_rcc_is_mckprot(void) 661 { 662 uintptr_t rcc_base = stm32mp_rcc_base(); 663 664 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0; 665 } 666 667 void stm32mp1_clk_rcc_regs_lock(void) 668 { 669 stm32mp1_clk_lock(®_lock); 670 } 671 672 void stm32mp1_clk_rcc_regs_unlock(void) 673 { 674 stm32mp1_clk_unlock(®_lock); 675 } 676 677 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 678 { 679 if (idx >= NB_OSC) { 680 return 0; 681 } 682 683 return stm32mp1_osc[idx]; 684 } 685 686 static int stm32mp1_clk_get_gated_id(unsigned long id) 687 { 688 unsigned int i; 689 690 for (i = 0U; i < NB_GATES; i++) { 691 if (gate_ref(i)->index == id) { 692 return i; 693 } 694 } 695 696 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 697 698 return -EINVAL; 699 } 700 701 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 702 { 703 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 704 } 705 706 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 707 { 708 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 709 } 710 711 static int stm32mp1_clk_get_parent(unsigned long id) 712 { 713 const struct stm32mp1_clk_sel *sel; 714 uint32_t p_sel; 715 int i; 716 enum stm32mp1_parent_id p; 717 enum stm32mp1_parent_sel s; 718 uintptr_t rcc_base = stm32mp_rcc_base(); 719 720 /* Few non gateable clock have a static parent ID, find them */ 721 i = (int)clock_id2parent_id(id); 722 if (i != _UNKNOWN_ID) { 723 return i; 724 } 725 726 i = stm32mp1_clk_get_gated_id(id); 727 if (i < 0) { 728 panic(); 729 } 730 731 p = stm32mp1_clk_get_fixed_parent(i); 732 if (p < _PARENT_NB) { 733 return (int)p; 734 } 735 736 s = stm32mp1_clk_get_sel(i); 737 if (s == _UNKNOWN_SEL) { 738 return -EINVAL; 739 } 740 if (s >= _PARENT_SEL_NB) { 741 panic(); 742 } 743 744 sel = clk_sel_ref(s); 745 p_sel = (mmio_read_32(rcc_base + sel->offset) & 746 (sel->msk << sel->src)) >> sel->src; 747 if (p_sel < sel->nb_parent) { 748 return (int)sel->parent[p_sel]; 749 } 750 751 return -EINVAL; 752 } 753 754 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 755 { 756 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 757 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 758 759 return stm32mp1_clk_get_fixed(pll->refclk[src]); 760 } 761 762 /* 763 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 764 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 765 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 766 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 767 */ 768 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 769 { 770 unsigned long refclk, fvco; 771 uint32_t cfgr1, fracr, divm, divn; 772 uintptr_t rcc_base = stm32mp_rcc_base(); 773 774 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 775 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 776 777 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 778 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 779 780 refclk = stm32mp1_pll_get_fref(pll); 781 782 /* 783 * With FRACV : 784 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 785 * Without FRACV 786 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 787 */ 788 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 789 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 790 RCC_PLLNFRACR_FRACV_SHIFT; 791 unsigned long long numerator, denominator; 792 793 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 794 numerator = refclk * numerator; 795 denominator = ((unsigned long long)divm + 1U) << 13; 796 fvco = (unsigned long)(numerator / denominator); 797 } else { 798 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 799 } 800 801 return fvco; 802 } 803 804 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 805 enum stm32mp1_div_id div_id) 806 { 807 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 808 unsigned long dfout; 809 uint32_t cfgr2, divy; 810 811 if (div_id >= _DIV_NB) { 812 return 0; 813 } 814 815 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 816 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 817 818 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 819 820 return dfout; 821 } 822 823 static unsigned long get_clock_rate(int p) 824 { 825 uint32_t reg, clkdiv; 826 unsigned long clock = 0; 827 uintptr_t rcc_base = stm32mp_rcc_base(); 828 829 switch (p) { 830 case _CK_MPU: 831 /* MPU sub system */ 832 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 833 switch (reg & RCC_SELR_SRC_MASK) { 834 case RCC_MPCKSELR_HSI: 835 clock = stm32mp1_clk_get_fixed(_HSI); 836 break; 837 case RCC_MPCKSELR_HSE: 838 clock = stm32mp1_clk_get_fixed(_HSE); 839 break; 840 case RCC_MPCKSELR_PLL: 841 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 842 break; 843 case RCC_MPCKSELR_PLL_MPUDIV: 844 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 845 846 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 847 clkdiv = reg & RCC_MPUDIV_MASK; 848 if (clkdiv != 0U) { 849 clock /= stm32mp1_mpu_div[clkdiv]; 850 } 851 break; 852 default: 853 break; 854 } 855 break; 856 /* AXI sub system */ 857 case _ACLK: 858 case _HCLK2: 859 case _HCLK6: 860 case _PCLK4: 861 case _PCLK5: 862 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 863 switch (reg & RCC_SELR_SRC_MASK) { 864 case RCC_ASSCKSELR_HSI: 865 clock = stm32mp1_clk_get_fixed(_HSI); 866 break; 867 case RCC_ASSCKSELR_HSE: 868 clock = stm32mp1_clk_get_fixed(_HSE); 869 break; 870 case RCC_ASSCKSELR_PLL: 871 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 872 break; 873 default: 874 break; 875 } 876 877 /* System clock divider */ 878 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 879 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 880 881 switch (p) { 882 case _PCLK4: 883 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 884 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 885 break; 886 case _PCLK5: 887 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 888 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 889 break; 890 default: 891 break; 892 } 893 break; 894 /* MCU sub system */ 895 case _CK_MCU: 896 case _PCLK1: 897 case _PCLK2: 898 case _PCLK3: 899 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 900 switch (reg & RCC_SELR_SRC_MASK) { 901 case RCC_MSSCKSELR_HSI: 902 clock = stm32mp1_clk_get_fixed(_HSI); 903 break; 904 case RCC_MSSCKSELR_HSE: 905 clock = stm32mp1_clk_get_fixed(_HSE); 906 break; 907 case RCC_MSSCKSELR_CSI: 908 clock = stm32mp1_clk_get_fixed(_CSI); 909 break; 910 case RCC_MSSCKSELR_PLL: 911 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 912 break; 913 default: 914 break; 915 } 916 917 /* MCU clock divider */ 918 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 919 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 920 921 switch (p) { 922 case _PCLK1: 923 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 924 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 925 break; 926 case _PCLK2: 927 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 928 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 929 break; 930 case _PCLK3: 931 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 932 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 933 break; 934 case _CK_MCU: 935 default: 936 break; 937 } 938 break; 939 case _CK_PER: 940 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 941 switch (reg & RCC_SELR_SRC_MASK) { 942 case RCC_CPERCKSELR_HSI: 943 clock = stm32mp1_clk_get_fixed(_HSI); 944 break; 945 case RCC_CPERCKSELR_HSE: 946 clock = stm32mp1_clk_get_fixed(_HSE); 947 break; 948 case RCC_CPERCKSELR_CSI: 949 clock = stm32mp1_clk_get_fixed(_CSI); 950 break; 951 default: 952 break; 953 } 954 break; 955 case _HSI: 956 case _HSI_KER: 957 clock = stm32mp1_clk_get_fixed(_HSI); 958 break; 959 case _CSI: 960 case _CSI_KER: 961 clock = stm32mp1_clk_get_fixed(_CSI); 962 break; 963 case _HSE: 964 case _HSE_KER: 965 clock = stm32mp1_clk_get_fixed(_HSE); 966 break; 967 case _HSE_KER_DIV2: 968 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 969 break; 970 case _LSI: 971 clock = stm32mp1_clk_get_fixed(_LSI); 972 break; 973 case _LSE: 974 clock = stm32mp1_clk_get_fixed(_LSE); 975 break; 976 /* PLL */ 977 case _PLL1_P: 978 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 979 break; 980 case _PLL1_Q: 981 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 982 break; 983 case _PLL1_R: 984 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 985 break; 986 case _PLL2_P: 987 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 988 break; 989 case _PLL2_Q: 990 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 991 break; 992 case _PLL2_R: 993 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 994 break; 995 case _PLL3_P: 996 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 997 break; 998 case _PLL3_Q: 999 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1000 break; 1001 case _PLL3_R: 1002 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1003 break; 1004 case _PLL4_P: 1005 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1006 break; 1007 case _PLL4_Q: 1008 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1009 break; 1010 case _PLL4_R: 1011 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1012 break; 1013 /* Other */ 1014 case _USB_PHY_48: 1015 clock = USB_PHY_48_MHZ; 1016 break; 1017 default: 1018 break; 1019 } 1020 1021 return clock; 1022 } 1023 1024 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1025 { 1026 uintptr_t rcc_base = stm32mp_rcc_base(); 1027 1028 VERBOSE("Enable clock %u\n", gate->index); 1029 1030 if (gate->set_clr != 0U) { 1031 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1032 } else { 1033 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1034 } 1035 } 1036 1037 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1038 { 1039 uintptr_t rcc_base = stm32mp_rcc_base(); 1040 1041 VERBOSE("Disable clock %u\n", gate->index); 1042 1043 if (gate->set_clr != 0U) { 1044 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1045 BIT(gate->bit)); 1046 } else { 1047 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1048 } 1049 } 1050 1051 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1052 { 1053 uintptr_t rcc_base = stm32mp_rcc_base(); 1054 1055 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1056 } 1057 1058 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 1059 { 1060 int i = stm32mp1_clk_get_gated_id(id); 1061 1062 if (i < 0) { 1063 panic(); 1064 } 1065 1066 return gate_refcounts[i]; 1067 } 1068 1069 /* Oscillators and PLLs are not gated at runtime */ 1070 static bool clock_is_always_on(unsigned long id) 1071 { 1072 switch (id) { 1073 case CK_HSE: 1074 case CK_CSI: 1075 case CK_LSI: 1076 case CK_LSE: 1077 case CK_HSI: 1078 case CK_HSE_DIV2: 1079 case PLL1_Q: 1080 case PLL1_R: 1081 case PLL2_P: 1082 case PLL2_Q: 1083 case PLL2_R: 1084 case PLL3_P: 1085 case PLL3_Q: 1086 case PLL3_R: 1087 return true; 1088 default: 1089 return false; 1090 } 1091 } 1092 1093 void __stm32mp1_clk_enable(unsigned long id, bool secure) 1094 { 1095 const struct stm32mp1_clk_gate *gate; 1096 int i; 1097 unsigned int *refcnt; 1098 1099 if (clock_is_always_on(id)) { 1100 return; 1101 } 1102 1103 i = stm32mp1_clk_get_gated_id(id); 1104 if (i < 0) { 1105 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 1106 panic(); 1107 } 1108 1109 gate = gate_ref(i); 1110 refcnt = &gate_refcounts[i]; 1111 1112 stm32mp1_clk_lock(&refcount_lock); 1113 1114 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 1115 __clk_enable(gate); 1116 } 1117 1118 stm32mp1_clk_unlock(&refcount_lock); 1119 } 1120 1121 void __stm32mp1_clk_disable(unsigned long id, bool secure) 1122 { 1123 const struct stm32mp1_clk_gate *gate; 1124 int i; 1125 unsigned int *refcnt; 1126 1127 if (clock_is_always_on(id)) { 1128 return; 1129 } 1130 1131 i = stm32mp1_clk_get_gated_id(id); 1132 if (i < 0) { 1133 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1134 panic(); 1135 } 1136 1137 gate = gate_ref(i); 1138 refcnt = &gate_refcounts[i]; 1139 1140 stm32mp1_clk_lock(&refcount_lock); 1141 1142 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1143 __clk_disable(gate); 1144 } 1145 1146 stm32mp1_clk_unlock(&refcount_lock); 1147 } 1148 1149 void stm32mp_clk_enable(unsigned long id) 1150 { 1151 __stm32mp1_clk_enable(id, true); 1152 } 1153 1154 void stm32mp_clk_disable(unsigned long id) 1155 { 1156 __stm32mp1_clk_disable(id, true); 1157 } 1158 1159 bool stm32mp_clk_is_enabled(unsigned long id) 1160 { 1161 int i; 1162 1163 if (clock_is_always_on(id)) { 1164 return true; 1165 } 1166 1167 i = stm32mp1_clk_get_gated_id(id); 1168 if (i < 0) { 1169 panic(); 1170 } 1171 1172 return __clk_is_enabled(gate_ref(i)); 1173 } 1174 1175 unsigned long stm32mp_clk_get_rate(unsigned long id) 1176 { 1177 int p = stm32mp1_clk_get_parent(id); 1178 1179 if (p < 0) { 1180 return 0; 1181 } 1182 1183 return get_clock_rate(p); 1184 } 1185 1186 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1187 { 1188 uintptr_t address = stm32mp_rcc_base() + offset; 1189 1190 if (enable) { 1191 mmio_setbits_32(address, mask_on); 1192 } else { 1193 mmio_clrbits_32(address, mask_on); 1194 } 1195 } 1196 1197 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1198 { 1199 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1200 uintptr_t address = stm32mp_rcc_base() + offset; 1201 1202 mmio_write_32(address, mask_on); 1203 } 1204 1205 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1206 { 1207 uint64_t timeout; 1208 uint32_t mask_test; 1209 uintptr_t address = stm32mp_rcc_base() + offset; 1210 1211 if (enable) { 1212 mask_test = mask_rdy; 1213 } else { 1214 mask_test = 0; 1215 } 1216 1217 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1218 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1219 if (timeout_elapsed(timeout)) { 1220 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1221 mask_rdy, address, enable, mmio_read_32(address)); 1222 return -ETIMEDOUT; 1223 } 1224 } 1225 1226 return 0; 1227 } 1228 1229 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1230 { 1231 uint32_t value; 1232 uintptr_t rcc_base = stm32mp_rcc_base(); 1233 1234 if (digbyp) { 1235 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1236 } 1237 1238 if (bypass || digbyp) { 1239 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1240 } 1241 1242 /* 1243 * Warning: not recommended to switch directly from "high drive" 1244 * to "medium low drive", and vice-versa. 1245 */ 1246 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1247 RCC_BDCR_LSEDRV_SHIFT; 1248 1249 while (value != lsedrv) { 1250 if (value > lsedrv) { 1251 value--; 1252 } else { 1253 value++; 1254 } 1255 1256 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1257 RCC_BDCR_LSEDRV_MASK, 1258 value << RCC_BDCR_LSEDRV_SHIFT); 1259 } 1260 1261 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1262 } 1263 1264 static void stm32mp1_lse_wait(void) 1265 { 1266 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1267 VERBOSE("%s: failed\n", __func__); 1268 } 1269 } 1270 1271 static void stm32mp1_lsi_set(bool enable) 1272 { 1273 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1274 1275 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1276 VERBOSE("%s: failed\n", __func__); 1277 } 1278 } 1279 1280 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1281 { 1282 uintptr_t rcc_base = stm32mp_rcc_base(); 1283 1284 if (digbyp) { 1285 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1286 } 1287 1288 if (bypass || digbyp) { 1289 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1290 } 1291 1292 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1293 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1294 VERBOSE("%s: failed\n", __func__); 1295 } 1296 1297 if (css) { 1298 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1299 } 1300 } 1301 1302 static void stm32mp1_csi_set(bool enable) 1303 { 1304 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1305 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1306 VERBOSE("%s: failed\n", __func__); 1307 } 1308 } 1309 1310 static void stm32mp1_hsi_set(bool enable) 1311 { 1312 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1313 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1314 VERBOSE("%s: failed\n", __func__); 1315 } 1316 } 1317 1318 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1319 { 1320 uint64_t timeout; 1321 uintptr_t rcc_base = stm32mp_rcc_base(); 1322 uintptr_t address = rcc_base + RCC_OCRDYR; 1323 1324 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1325 RCC_HSICFGR_HSIDIV_MASK, 1326 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1327 1328 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1329 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1330 if (timeout_elapsed(timeout)) { 1331 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1332 address, mmio_read_32(address)); 1333 return -ETIMEDOUT; 1334 } 1335 } 1336 1337 return 0; 1338 } 1339 1340 static int stm32mp1_hsidiv(unsigned long hsifreq) 1341 { 1342 uint8_t hsidiv; 1343 uint32_t hsidivfreq = MAX_HSI_HZ; 1344 1345 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1346 if (hsidivfreq == hsifreq) { 1347 break; 1348 } 1349 1350 hsidivfreq /= 2U; 1351 } 1352 1353 if (hsidiv == 4U) { 1354 ERROR("Invalid clk-hsi frequency\n"); 1355 return -1; 1356 } 1357 1358 if (hsidiv != 0U) { 1359 return stm32mp1_set_hsidiv(hsidiv); 1360 } 1361 1362 return 0; 1363 } 1364 1365 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1366 unsigned int clksrc, 1367 uint32_t *pllcfg, int plloff) 1368 { 1369 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1370 uintptr_t rcc_base = stm32mp_rcc_base(); 1371 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1372 enum stm32mp1_plltype type = pll->plltype; 1373 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1374 unsigned long refclk; 1375 uint32_t ifrge = 0U; 1376 uint32_t src, value, fracv = 0; 1377 void *fdt; 1378 1379 /* Check PLL output */ 1380 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1381 return false; 1382 } 1383 1384 /* Check current clksrc */ 1385 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1386 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1387 return false; 1388 } 1389 1390 /* Check Div */ 1391 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1392 1393 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1394 (pllcfg[PLLCFG_M] + 1U); 1395 1396 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1397 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1398 return false; 1399 } 1400 1401 if ((type == PLL_800) && (refclk >= 8000000U)) { 1402 ifrge = 1U; 1403 } 1404 1405 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1406 RCC_PLLNCFGR1_DIVN_MASK; 1407 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1408 RCC_PLLNCFGR1_DIVM_MASK; 1409 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1410 RCC_PLLNCFGR1_IFRGE_MASK; 1411 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1412 return false; 1413 } 1414 1415 /* Fractional configuration */ 1416 if (fdt_get_address(&fdt) == 1) { 1417 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1418 } 1419 1420 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1421 value |= RCC_PLLNFRACR_FRACLE; 1422 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1423 return false; 1424 } 1425 1426 /* Output config */ 1427 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1428 RCC_PLLNCFGR2_DIVP_MASK; 1429 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1430 RCC_PLLNCFGR2_DIVQ_MASK; 1431 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1432 RCC_PLLNCFGR2_DIVR_MASK; 1433 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1434 return false; 1435 } 1436 1437 return true; 1438 } 1439 1440 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1441 { 1442 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1443 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1444 1445 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1446 mmio_clrsetbits_32(pllxcr, 1447 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1448 RCC_PLLNCR_DIVREN, 1449 RCC_PLLNCR_PLLON); 1450 } 1451 1452 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1453 { 1454 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1455 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1456 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1457 1458 /* Wait PLL lock */ 1459 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1460 if (timeout_elapsed(timeout)) { 1461 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1462 pll_id, pllxcr, mmio_read_32(pllxcr)); 1463 return -ETIMEDOUT; 1464 } 1465 } 1466 1467 /* Start the requested output */ 1468 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1469 1470 return 0; 1471 } 1472 1473 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1474 { 1475 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1476 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1477 uint64_t timeout; 1478 1479 /* Stop all output */ 1480 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1481 RCC_PLLNCR_DIVREN); 1482 1483 /* Stop PLL */ 1484 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1485 1486 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1487 /* Wait PLL stopped */ 1488 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1489 if (timeout_elapsed(timeout)) { 1490 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1491 pll_id, pllxcr, mmio_read_32(pllxcr)); 1492 return -ETIMEDOUT; 1493 } 1494 } 1495 1496 return 0; 1497 } 1498 1499 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1500 uint32_t *pllcfg) 1501 { 1502 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1503 uintptr_t rcc_base = stm32mp_rcc_base(); 1504 uint32_t value; 1505 1506 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1507 RCC_PLLNCFGR2_DIVP_MASK; 1508 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1509 RCC_PLLNCFGR2_DIVQ_MASK; 1510 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1511 RCC_PLLNCFGR2_DIVR_MASK; 1512 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1513 } 1514 1515 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1516 uint32_t *pllcfg, uint32_t fracv) 1517 { 1518 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1519 uintptr_t rcc_base = stm32mp_rcc_base(); 1520 enum stm32mp1_plltype type = pll->plltype; 1521 unsigned long refclk; 1522 uint32_t ifrge = 0; 1523 uint32_t src, value; 1524 1525 src = mmio_read_32(rcc_base + pll->rckxselr) & 1526 RCC_SELR_REFCLK_SRC_MASK; 1527 1528 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1529 (pllcfg[PLLCFG_M] + 1U); 1530 1531 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1532 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1533 return -EINVAL; 1534 } 1535 1536 if ((type == PLL_800) && (refclk >= 8000000U)) { 1537 ifrge = 1U; 1538 } 1539 1540 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1541 RCC_PLLNCFGR1_DIVN_MASK; 1542 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1543 RCC_PLLNCFGR1_DIVM_MASK; 1544 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1545 RCC_PLLNCFGR1_IFRGE_MASK; 1546 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1547 1548 /* Fractional configuration */ 1549 value = 0; 1550 mmio_write_32(rcc_base + pll->pllxfracr, value); 1551 1552 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1553 mmio_write_32(rcc_base + pll->pllxfracr, value); 1554 1555 value |= RCC_PLLNFRACR_FRACLE; 1556 mmio_write_32(rcc_base + pll->pllxfracr, value); 1557 1558 stm32mp1_pll_config_output(pll_id, pllcfg); 1559 1560 return 0; 1561 } 1562 1563 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1564 { 1565 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1566 uint32_t pllxcsg = 0; 1567 1568 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1569 RCC_PLLNCSGR_MOD_PER_MASK; 1570 1571 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1572 RCC_PLLNCSGR_INC_STEP_MASK; 1573 1574 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1575 RCC_PLLNCSGR_SSCG_MODE_MASK; 1576 1577 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1578 1579 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1580 RCC_PLLNCR_SSCG_CTRL); 1581 } 1582 1583 static int stm32mp1_set_clksrc(unsigned int clksrc) 1584 { 1585 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1586 uint64_t timeout; 1587 1588 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1589 clksrc & RCC_SELR_SRC_MASK); 1590 1591 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1592 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1593 if (timeout_elapsed(timeout)) { 1594 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1595 clksrc_address, mmio_read_32(clksrc_address)); 1596 return -ETIMEDOUT; 1597 } 1598 } 1599 1600 return 0; 1601 } 1602 1603 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1604 { 1605 uint64_t timeout; 1606 1607 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1608 clkdiv & RCC_DIVR_DIV_MASK); 1609 1610 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1611 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1612 if (timeout_elapsed(timeout)) { 1613 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1614 clkdiv, address, mmio_read_32(address)); 1615 return -ETIMEDOUT; 1616 } 1617 } 1618 1619 return 0; 1620 } 1621 1622 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1623 { 1624 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1625 1626 /* 1627 * Binding clksrc : 1628 * bit15-4 offset 1629 * bit3: disable 1630 * bit2-0: MCOSEL[2:0] 1631 */ 1632 if ((clksrc & 0x8U) != 0U) { 1633 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1634 } else { 1635 mmio_clrsetbits_32(clksrc_address, 1636 RCC_MCOCFG_MCOSRC_MASK, 1637 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1638 mmio_clrsetbits_32(clksrc_address, 1639 RCC_MCOCFG_MCODIV_MASK, 1640 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1641 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1642 } 1643 } 1644 1645 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1646 { 1647 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1648 1649 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1650 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1651 mmio_clrsetbits_32(address, 1652 RCC_BDCR_RTCSRC_MASK, 1653 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1654 1655 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1656 } 1657 1658 if (lse_css) { 1659 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1660 } 1661 } 1662 1663 static void stm32mp1_stgen_config(void) 1664 { 1665 uintptr_t stgen; 1666 uint32_t cntfid0; 1667 unsigned long rate; 1668 unsigned long long counter; 1669 1670 stgen = fdt_get_stgen_base(); 1671 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1672 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1673 1674 if (cntfid0 == rate) { 1675 return; 1676 } 1677 1678 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1679 counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); 1680 counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; 1681 counter = (counter * rate / cntfid0); 1682 1683 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1684 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1685 mmio_write_32(stgen + CNTFID_OFF, rate); 1686 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1687 1688 write_cntfrq((u_register_t)rate); 1689 1690 /* Need to update timer with new frequency */ 1691 generic_delay_timer_init(); 1692 } 1693 1694 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1695 { 1696 uintptr_t stgen; 1697 unsigned long long cnt; 1698 1699 stgen = fdt_get_stgen_base(); 1700 1701 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1702 mmio_read_32(stgen + CNTCVL_OFF); 1703 1704 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1705 1706 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1707 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1708 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1709 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1710 } 1711 1712 static void stm32mp1_pkcs_config(uint32_t pkcs) 1713 { 1714 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1715 uint32_t value = pkcs & 0xFU; 1716 uint32_t mask = 0xFU; 1717 1718 if ((pkcs & BIT(31)) != 0U) { 1719 mask <<= 4; 1720 value <<= 4; 1721 } 1722 1723 mmio_clrsetbits_32(address, mask, value); 1724 } 1725 1726 int stm32mp1_clk_init(void) 1727 { 1728 uintptr_t rcc_base = stm32mp_rcc_base(); 1729 unsigned int clksrc[CLKSRC_NB]; 1730 unsigned int clkdiv[CLKDIV_NB]; 1731 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1732 int plloff[_PLL_NB]; 1733 int ret, len; 1734 enum stm32mp1_pll_id i; 1735 bool lse_css = false; 1736 bool pll3_preserve = false; 1737 bool pll4_preserve = false; 1738 bool pll4_bootrom = false; 1739 const fdt32_t *pkcs_cell; 1740 void *fdt; 1741 1742 if (fdt_get_address(&fdt) == 0) { 1743 return false; 1744 } 1745 1746 /* Check status field to disable security */ 1747 if (!fdt_get_rcc_secure_status()) { 1748 mmio_write_32(rcc_base + RCC_TZCR, 0); 1749 } 1750 1751 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1752 clksrc); 1753 if (ret < 0) { 1754 return -FDT_ERR_NOTFOUND; 1755 } 1756 1757 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1758 clkdiv); 1759 if (ret < 0) { 1760 return -FDT_ERR_NOTFOUND; 1761 } 1762 1763 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1764 char name[12]; 1765 1766 snprintf(name, sizeof(name), "st,pll@%d", i); 1767 plloff[i] = fdt_rcc_subnode_offset(name); 1768 1769 if (!fdt_check_node(plloff[i])) { 1770 continue; 1771 } 1772 1773 ret = fdt_read_uint32_array(fdt, plloff[i], "cfg", 1774 (int)PLLCFG_NB, pllcfg[i]); 1775 if (ret < 0) { 1776 return -FDT_ERR_NOTFOUND; 1777 } 1778 } 1779 1780 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1781 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1782 1783 /* 1784 * Switch ON oscillator found in device-tree. 1785 * Note: HSI already ON after BootROM stage. 1786 */ 1787 if (stm32mp1_osc[_LSI] != 0U) { 1788 stm32mp1_lsi_set(true); 1789 } 1790 if (stm32mp1_osc[_LSE] != 0U) { 1791 bool bypass, digbyp; 1792 uint32_t lsedrv; 1793 1794 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1795 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1796 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1797 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1798 LSEDRV_MEDIUM_HIGH); 1799 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1800 } 1801 if (stm32mp1_osc[_HSE] != 0U) { 1802 bool bypass, digbyp, css; 1803 1804 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1805 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1806 css = fdt_osc_read_bool(_HSE, "st,css"); 1807 stm32mp1_hse_enable(bypass, digbyp, css); 1808 } 1809 /* 1810 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1811 * => switch on CSI even if node is not present in device tree 1812 */ 1813 stm32mp1_csi_set(true); 1814 1815 /* Come back to HSI */ 1816 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1817 if (ret != 0) { 1818 return ret; 1819 } 1820 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1821 if (ret != 0) { 1822 return ret; 1823 } 1824 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1825 if (ret != 0) { 1826 return ret; 1827 } 1828 1829 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1830 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1831 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1832 clksrc[CLKSRC_PLL3], 1833 pllcfg[_PLL3], 1834 plloff[_PLL3]); 1835 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1836 clksrc[CLKSRC_PLL4], 1837 pllcfg[_PLL4], 1838 plloff[_PLL4]); 1839 } 1840 1841 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1842 if (((i == _PLL3) && pll3_preserve) || 1843 ((i == _PLL4) && pll4_preserve)) { 1844 continue; 1845 } 1846 1847 ret = stm32mp1_pll_stop(i); 1848 if (ret != 0) { 1849 return ret; 1850 } 1851 } 1852 1853 /* Configure HSIDIV */ 1854 if (stm32mp1_osc[_HSI] != 0U) { 1855 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1856 if (ret != 0) { 1857 return ret; 1858 } 1859 stm32mp1_stgen_config(); 1860 } 1861 1862 /* Select DIV */ 1863 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1864 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1865 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1866 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1867 if (ret != 0) { 1868 return ret; 1869 } 1870 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1871 if (ret != 0) { 1872 return ret; 1873 } 1874 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1875 if (ret != 0) { 1876 return ret; 1877 } 1878 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1879 if (ret != 0) { 1880 return ret; 1881 } 1882 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1883 if (ret != 0) { 1884 return ret; 1885 } 1886 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1887 if (ret != 0) { 1888 return ret; 1889 } 1890 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1891 if (ret != 0) { 1892 return ret; 1893 } 1894 1895 /* No ready bit for RTC */ 1896 mmio_write_32(rcc_base + RCC_RTCDIVR, 1897 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1898 1899 /* Configure PLLs source */ 1900 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1901 if (ret != 0) { 1902 return ret; 1903 } 1904 1905 if (!pll3_preserve) { 1906 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1907 if (ret != 0) { 1908 return ret; 1909 } 1910 } 1911 1912 if (!pll4_preserve) { 1913 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1914 if (ret != 0) { 1915 return ret; 1916 } 1917 } 1918 1919 /* Configure and start PLLs */ 1920 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1921 uint32_t fracv; 1922 uint32_t csg[PLLCSG_NB]; 1923 1924 if (((i == _PLL3) && pll3_preserve) || 1925 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1926 continue; 1927 } 1928 1929 if (!fdt_check_node(plloff[i])) { 1930 continue; 1931 } 1932 1933 if ((i == _PLL4) && pll4_bootrom) { 1934 /* Set output divider if not done by the Bootrom */ 1935 stm32mp1_pll_config_output(i, pllcfg[i]); 1936 continue; 1937 } 1938 1939 fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0); 1940 1941 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 1942 if (ret != 0) { 1943 return ret; 1944 } 1945 ret = fdt_read_uint32_array(fdt, plloff[i], "csg", 1946 (uint32_t)PLLCSG_NB, csg); 1947 if (ret == 0) { 1948 stm32mp1_pll_csg(i, csg); 1949 } else if (ret != -FDT_ERR_NOTFOUND) { 1950 return ret; 1951 } 1952 1953 stm32mp1_pll_start(i); 1954 } 1955 /* Wait and start PLLs ouptut when ready */ 1956 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1957 if (!fdt_check_node(plloff[i])) { 1958 continue; 1959 } 1960 1961 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 1962 if (ret != 0) { 1963 return ret; 1964 } 1965 } 1966 /* Wait LSE ready before to use it */ 1967 if (stm32mp1_osc[_LSE] != 0U) { 1968 stm32mp1_lse_wait(); 1969 } 1970 1971 /* Configure with expected clock source */ 1972 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 1973 if (ret != 0) { 1974 return ret; 1975 } 1976 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 1977 if (ret != 0) { 1978 return ret; 1979 } 1980 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 1981 if (ret != 0) { 1982 return ret; 1983 } 1984 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 1985 1986 /* Configure PKCK */ 1987 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1988 if (pkcs_cell != NULL) { 1989 bool ckper_disabled = false; 1990 uint32_t j; 1991 1992 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1993 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1994 1995 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1996 ckper_disabled = true; 1997 continue; 1998 } 1999 stm32mp1_pkcs_config(pkcs); 2000 } 2001 2002 /* 2003 * CKPER is source for some peripheral clocks 2004 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2005 * only if previous clock is still ON 2006 * => deactivated CKPER only after switching clock 2007 */ 2008 if (ckper_disabled) { 2009 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2010 } 2011 } 2012 2013 /* Switch OFF HSI if not found in device-tree */ 2014 if (stm32mp1_osc[_HSI] == 0U) { 2015 stm32mp1_hsi_set(false); 2016 } 2017 stm32mp1_stgen_config(); 2018 2019 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2020 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2021 RCC_DDRITFCR_DDRCKMOD_MASK, 2022 RCC_DDRITFCR_DDRCKMOD_SSR << 2023 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2024 2025 return 0; 2026 } 2027 2028 static void stm32mp1_osc_clk_init(const char *name, 2029 enum stm32mp_osc_id index) 2030 { 2031 uint32_t frequency; 2032 2033 if (fdt_osc_read_freq(name, &frequency) == 0) { 2034 stm32mp1_osc[index] = frequency; 2035 } 2036 } 2037 2038 static void stm32mp1_osc_init(void) 2039 { 2040 enum stm32mp_osc_id i; 2041 2042 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2043 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2044 } 2045 } 2046 2047 #ifdef STM32MP_SHARED_RESOURCES 2048 /* 2049 * Get the parent ID of the target parent clock, for tagging as secure 2050 * shared clock dependencies. 2051 */ 2052 static int get_parent_id_parent(unsigned int parent_id) 2053 { 2054 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2055 enum stm32mp1_pll_id pll_id; 2056 uint32_t p_sel; 2057 uintptr_t rcc_base = stm32mp_rcc_base(); 2058 2059 switch (parent_id) { 2060 case _ACLK: 2061 case _PCLK4: 2062 case _PCLK5: 2063 s = _AXIS_SEL; 2064 break; 2065 case _PLL1_P: 2066 case _PLL1_Q: 2067 case _PLL1_R: 2068 pll_id = _PLL1; 2069 break; 2070 case _PLL2_P: 2071 case _PLL2_Q: 2072 case _PLL2_R: 2073 pll_id = _PLL2; 2074 break; 2075 case _PLL3_P: 2076 case _PLL3_Q: 2077 case _PLL3_R: 2078 pll_id = _PLL3; 2079 break; 2080 case _PLL4_P: 2081 case _PLL4_Q: 2082 case _PLL4_R: 2083 pll_id = _PLL4; 2084 break; 2085 case _PCLK1: 2086 case _PCLK2: 2087 case _HCLK2: 2088 case _HCLK6: 2089 case _CK_PER: 2090 case _CK_MPU: 2091 case _CK_MCU: 2092 case _USB_PHY_48: 2093 /* We do not expect to access these */ 2094 panic(); 2095 break; 2096 default: 2097 /* Other parents have no parent */ 2098 return -1; 2099 } 2100 2101 if (s != _UNKNOWN_SEL) { 2102 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2103 2104 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2105 sel->msk; 2106 2107 if (p_sel < sel->nb_parent) { 2108 return (int)sel->parent[p_sel]; 2109 } 2110 } else { 2111 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2112 2113 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2114 RCC_SELR_REFCLK_SRC_MASK; 2115 2116 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2117 return (int)pll->refclk[p_sel]; 2118 } 2119 } 2120 2121 VERBOSE("No parent selected for %s\n", 2122 stm32mp1_clk_parent_name[parent_id]); 2123 2124 return -1; 2125 } 2126 2127 static void secure_parent_clocks(unsigned long parent_id) 2128 { 2129 int grandparent_id; 2130 2131 switch (parent_id) { 2132 case _PLL3_P: 2133 case _PLL3_Q: 2134 case _PLL3_R: 2135 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2136 break; 2137 2138 /* These clocks are always secure when RCC is secure */ 2139 case _ACLK: 2140 case _HCLK2: 2141 case _HCLK6: 2142 case _PCLK4: 2143 case _PCLK5: 2144 case _PLL1_P: 2145 case _PLL1_Q: 2146 case _PLL1_R: 2147 case _PLL2_P: 2148 case _PLL2_Q: 2149 case _PLL2_R: 2150 case _HSI: 2151 case _HSI_KER: 2152 case _LSI: 2153 case _CSI: 2154 case _CSI_KER: 2155 case _HSE: 2156 case _HSE_KER: 2157 case _HSE_KER_DIV2: 2158 case _LSE: 2159 break; 2160 2161 default: 2162 VERBOSE("Cannot secure parent clock %s\n", 2163 stm32mp1_clk_parent_name[parent_id]); 2164 panic(); 2165 } 2166 2167 grandparent_id = get_parent_id_parent(parent_id); 2168 if (grandparent_id >= 0) { 2169 secure_parent_clocks(grandparent_id); 2170 } 2171 } 2172 2173 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2174 { 2175 int parent_id; 2176 2177 if (!stm32mp1_rcc_is_secure()) { 2178 return; 2179 } 2180 2181 switch (clock_id) { 2182 case PLL1: 2183 case PLL2: 2184 /* PLL1/PLL2 are always secure: nothing to do */ 2185 break; 2186 case PLL3: 2187 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2188 break; 2189 case PLL4: 2190 ERROR("PLL4 cannot be secured\n"); 2191 panic(); 2192 break; 2193 default: 2194 /* Others are expected gateable clock */ 2195 parent_id = stm32mp1_clk_get_parent(clock_id); 2196 if (parent_id < 0) { 2197 INFO("No parent found for clock %lu\n", clock_id); 2198 } else { 2199 secure_parent_clocks(parent_id); 2200 } 2201 break; 2202 } 2203 } 2204 #endif /* STM32MP_SHARED_RESOURCES */ 2205 2206 static void sync_earlyboot_clocks_state(void) 2207 { 2208 unsigned int idx; 2209 const unsigned long secure_enable[] = { 2210 AXIDCG, 2211 BSEC, 2212 DDRC1, DDRC1LP, 2213 DDRC2, DDRC2LP, 2214 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2215 DDRPHYC, DDRPHYCLP, 2216 TZC1, TZC2, 2217 TZPC, 2218 STGEN_K, 2219 }; 2220 2221 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2222 stm32mp_clk_enable(secure_enable[idx]); 2223 } 2224 2225 if (!stm32mp_is_single_core()) { 2226 stm32mp1_clk_enable_secure(RTCAPB); 2227 } 2228 } 2229 2230 int stm32mp1_clk_probe(void) 2231 { 2232 stm32mp1_osc_init(); 2233 2234 sync_earlyboot_clocks_state(); 2235 2236 return 0; 2237 } 2238