1 /* 2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <common/fdt_wrappers.h> 20 #include <drivers/delay_timer.h> 21 #include <drivers/generic_delay_timer.h> 22 #include <drivers/st/stm32mp_clkfunc.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_rcc.h> 25 #include <dt-bindings/clock/stm32mp1-clksrc.h> 26 #include <lib/mmio.h> 27 #include <lib/spinlock.h> 28 #include <lib/utils_def.h> 29 #include <plat/common/platform.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _CSI_KER, 60 _PLL1_P, 61 _PLL1_Q, 62 _PLL1_R, 63 _PLL2_P, 64 _PLL2_Q, 65 _PLL2_R, 66 _PLL3_P, 67 _PLL3_Q, 68 _PLL3_R, 69 _PLL4_P, 70 _PLL4_Q, 71 _PLL4_R, 72 _ACLK, 73 _PCLK1, 74 _PCLK2, 75 _PCLK3, 76 _PCLK4, 77 _PCLK5, 78 _HCLK6, 79 _HCLK2, 80 _CK_PER, 81 _CK_MPU, 82 _CK_MCU, 83 _USB_PHY_48, 84 _PARENT_NB, 85 _UNKNOWN_ID = 0xff, 86 }; 87 88 /* Lists only the parent clock we are interested in */ 89 enum stm32mp1_parent_sel { 90 _I2C12_SEL, 91 _I2C35_SEL, 92 _STGEN_SEL, 93 _I2C46_SEL, 94 _SPI6_SEL, 95 _UART1_SEL, 96 _RNG1_SEL, 97 _UART6_SEL, 98 _UART24_SEL, 99 _UART35_SEL, 100 _UART78_SEL, 101 _SDMMC12_SEL, 102 _SDMMC3_SEL, 103 _QSPI_SEL, 104 _FMC_SEL, 105 _AXIS_SEL, 106 _MCUS_SEL, 107 _USBPHY_SEL, 108 _USBO_SEL, 109 _PARENT_SEL_NB, 110 _UNKNOWN_SEL = 0xff, 111 }; 112 113 enum stm32mp1_pll_id { 114 _PLL1, 115 _PLL2, 116 _PLL3, 117 _PLL4, 118 _PLL_NB 119 }; 120 121 enum stm32mp1_div_id { 122 _DIV_P, 123 _DIV_Q, 124 _DIV_R, 125 _DIV_NB, 126 }; 127 128 enum stm32mp1_clksrc_id { 129 CLKSRC_MPU, 130 CLKSRC_AXI, 131 CLKSRC_MCU, 132 CLKSRC_PLL12, 133 CLKSRC_PLL3, 134 CLKSRC_PLL4, 135 CLKSRC_RTC, 136 CLKSRC_MCO1, 137 CLKSRC_MCO2, 138 CLKSRC_NB 139 }; 140 141 enum stm32mp1_clkdiv_id { 142 CLKDIV_MPU, 143 CLKDIV_AXI, 144 CLKDIV_MCU, 145 CLKDIV_APB1, 146 CLKDIV_APB2, 147 CLKDIV_APB3, 148 CLKDIV_APB4, 149 CLKDIV_APB5, 150 CLKDIV_RTC, 151 CLKDIV_MCO1, 152 CLKDIV_MCO2, 153 CLKDIV_NB 154 }; 155 156 enum stm32mp1_pllcfg { 157 PLLCFG_M, 158 PLLCFG_N, 159 PLLCFG_P, 160 PLLCFG_Q, 161 PLLCFG_R, 162 PLLCFG_O, 163 PLLCFG_NB 164 }; 165 166 enum stm32mp1_pllcsg { 167 PLLCSG_MOD_PER, 168 PLLCSG_INC_STEP, 169 PLLCSG_SSCG_MODE, 170 PLLCSG_NB 171 }; 172 173 enum stm32mp1_plltype { 174 PLL_800, 175 PLL_1600, 176 PLL_TYPE_NB 177 }; 178 179 struct stm32mp1_pll { 180 uint8_t refclk_min; 181 uint8_t refclk_max; 182 uint8_t divn_max; 183 }; 184 185 struct stm32mp1_clk_gate { 186 uint16_t offset; 187 uint8_t bit; 188 uint8_t index; 189 uint8_t set_clr; 190 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 191 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 192 }; 193 194 struct stm32mp1_clk_sel { 195 uint16_t offset; 196 uint8_t src; 197 uint8_t msk; 198 uint8_t nb_parent; 199 const uint8_t *parent; 200 }; 201 202 #define REFCLK_SIZE 4 203 struct stm32mp1_clk_pll { 204 enum stm32mp1_plltype plltype; 205 uint16_t rckxselr; 206 uint16_t pllxcfgr1; 207 uint16_t pllxcfgr2; 208 uint16_t pllxfracr; 209 uint16_t pllxcr; 210 uint16_t pllxcsgr; 211 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 212 }; 213 214 /* Clocks with selectable source and non set/clr register access */ 215 #define _CLK_SELEC(off, b, idx, s) \ 216 { \ 217 .offset = (off), \ 218 .bit = (b), \ 219 .index = (idx), \ 220 .set_clr = 0, \ 221 .sel = (s), \ 222 .fixed = _UNKNOWN_ID, \ 223 } 224 225 /* Clocks with fixed source and non set/clr register access */ 226 #define _CLK_FIXED(off, b, idx, f) \ 227 { \ 228 .offset = (off), \ 229 .bit = (b), \ 230 .index = (idx), \ 231 .set_clr = 0, \ 232 .sel = _UNKNOWN_SEL, \ 233 .fixed = (f), \ 234 } 235 236 /* Clocks with selectable source and set/clr register access */ 237 #define _CLK_SC_SELEC(off, b, idx, s) \ 238 { \ 239 .offset = (off), \ 240 .bit = (b), \ 241 .index = (idx), \ 242 .set_clr = 1, \ 243 .sel = (s), \ 244 .fixed = _UNKNOWN_ID, \ 245 } 246 247 /* Clocks with fixed source and set/clr register access */ 248 #define _CLK_SC_FIXED(off, b, idx, f) \ 249 { \ 250 .offset = (off), \ 251 .bit = (b), \ 252 .index = (idx), \ 253 .set_clr = 1, \ 254 .sel = _UNKNOWN_SEL, \ 255 .fixed = (f), \ 256 } 257 258 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 259 [_ ## _label ## _SEL] = { \ 260 .offset = _rcc_selr, \ 261 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 262 .msk = _rcc_selr ## _ ## _label ## SRC_MASK, \ 263 .parent = (_parents), \ 264 .nb_parent = ARRAY_SIZE(_parents) \ 265 } 266 267 #define _CLK_PLL(idx, type, off1, off2, off3, \ 268 off4, off5, off6, \ 269 p1, p2, p3, p4) \ 270 [(idx)] = { \ 271 .plltype = (type), \ 272 .rckxselr = (off1), \ 273 .pllxcfgr1 = (off2), \ 274 .pllxcfgr2 = (off3), \ 275 .pllxfracr = (off4), \ 276 .pllxcr = (off5), \ 277 .pllxcsgr = (off6), \ 278 .refclk[0] = (p1), \ 279 .refclk[1] = (p2), \ 280 .refclk[2] = (p3), \ 281 .refclk[3] = (p4), \ 282 } 283 284 static const uint8_t stm32mp1_clks[][2] = { 285 { CK_PER, _CK_PER }, 286 { CK_MPU, _CK_MPU }, 287 { CK_AXI, _ACLK }, 288 { CK_MCU, _CK_MCU }, 289 { CK_HSE, _HSE }, 290 { CK_CSI, _CSI }, 291 { CK_LSI, _LSI }, 292 { CK_LSE, _LSE }, 293 { CK_HSI, _HSI }, 294 { CK_HSE_DIV2, _HSE_KER_DIV2 }, 295 }; 296 297 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 298 299 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 300 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 301 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 302 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 303 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 304 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 305 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 306 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 307 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 308 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 309 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 310 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 311 312 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 313 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 314 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 315 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 316 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 317 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 318 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 319 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 320 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 321 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 322 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 323 324 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 325 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 326 327 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 328 329 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 330 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 331 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 332 333 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 334 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 335 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 336 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 337 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 338 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 339 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 340 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 341 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 342 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 343 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 344 345 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 346 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 347 348 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 349 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 350 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 351 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 352 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 353 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 354 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 355 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 356 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 357 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 358 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 359 360 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 361 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 362 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 363 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 364 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 365 366 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 367 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 368 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 369 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 370 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 371 372 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 373 }; 374 375 static const uint8_t i2c12_parents[] = { 376 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 377 }; 378 379 static const uint8_t i2c35_parents[] = { 380 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 381 }; 382 383 static const uint8_t stgen_parents[] = { 384 _HSI_KER, _HSE_KER 385 }; 386 387 static const uint8_t i2c46_parents[] = { 388 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 389 }; 390 391 static const uint8_t spi6_parents[] = { 392 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 393 }; 394 395 static const uint8_t usart1_parents[] = { 396 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 397 }; 398 399 static const uint8_t rng1_parents[] = { 400 _CSI, _PLL4_R, _LSE, _LSI 401 }; 402 403 static const uint8_t uart6_parents[] = { 404 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 405 }; 406 407 static const uint8_t uart234578_parents[] = { 408 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 409 }; 410 411 static const uint8_t sdmmc12_parents[] = { 412 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 413 }; 414 415 static const uint8_t sdmmc3_parents[] = { 416 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 417 }; 418 419 static const uint8_t qspi_parents[] = { 420 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 421 }; 422 423 static const uint8_t fmc_parents[] = { 424 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 425 }; 426 427 static const uint8_t ass_parents[] = { 428 _HSI, _HSE, _PLL2 429 }; 430 431 static const uint8_t mss_parents[] = { 432 _HSI, _HSE, _CSI, _PLL3 433 }; 434 435 static const uint8_t usbphy_parents[] = { 436 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 437 }; 438 439 static const uint8_t usbo_parents[] = { 440 _PLL4_R, _USB_PHY_48 441 }; 442 443 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 444 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 445 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 446 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 447 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 448 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 449 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 450 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 451 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 452 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 453 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 454 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 455 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 456 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 457 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 458 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 459 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents), 460 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents), 461 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 462 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 463 }; 464 465 /* Define characteristic of PLL according type */ 466 #define DIVN_MIN 24 467 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 468 [PLL_800] = { 469 .refclk_min = 4, 470 .refclk_max = 16, 471 .divn_max = 99, 472 }, 473 [PLL_1600] = { 474 .refclk_min = 8, 475 .refclk_max = 16, 476 .divn_max = 199, 477 }, 478 }; 479 480 /* PLLNCFGR2 register divider by output */ 481 static const uint8_t pllncfgr2[_DIV_NB] = { 482 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 483 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 484 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 485 }; 486 487 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 488 _CLK_PLL(_PLL1, PLL_1600, 489 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 490 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 491 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 492 _CLK_PLL(_PLL2, PLL_1600, 493 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 494 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 495 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 496 _CLK_PLL(_PLL3, PLL_800, 497 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 498 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 499 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 500 _CLK_PLL(_PLL4, PLL_800, 501 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 502 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 503 _HSI, _HSE, _CSI, _I2S_CKIN), 504 }; 505 506 /* Prescaler table lookups for clock computation */ 507 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 508 static const uint8_t stm32mp1_mcu_div[16] = { 509 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 510 }; 511 512 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 513 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 514 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 515 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 516 0, 1, 2, 3, 4, 4, 4, 4 517 }; 518 519 /* div = /1 /2 /3 /4 */ 520 static const uint8_t stm32mp1_axi_div[8] = { 521 1, 2, 3, 4, 4, 4, 4, 4 522 }; 523 524 /* RCC clock device driver private */ 525 static unsigned long stm32mp1_osc[NB_OSC]; 526 static struct spinlock reg_lock; 527 static unsigned int gate_refcounts[NB_GATES]; 528 static struct spinlock refcount_lock; 529 530 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 531 { 532 return &stm32mp1_clk_gate[idx]; 533 } 534 535 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 536 { 537 return &stm32mp1_clk_sel[idx]; 538 } 539 540 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 541 { 542 return &stm32mp1_clk_pll[idx]; 543 } 544 545 static void stm32mp1_clk_lock(struct spinlock *lock) 546 { 547 if (stm32mp_lock_available()) { 548 /* Assume interrupts are masked */ 549 spin_lock(lock); 550 } 551 } 552 553 static void stm32mp1_clk_unlock(struct spinlock *lock) 554 { 555 if (stm32mp_lock_available()) { 556 spin_unlock(lock); 557 } 558 } 559 560 bool stm32mp1_rcc_is_secure(void) 561 { 562 uintptr_t rcc_base = stm32mp_rcc_base(); 563 564 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0; 565 } 566 567 bool stm32mp1_rcc_is_mckprot(void) 568 { 569 uintptr_t rcc_base = stm32mp_rcc_base(); 570 571 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0; 572 } 573 574 void stm32mp1_clk_rcc_regs_lock(void) 575 { 576 stm32mp1_clk_lock(®_lock); 577 } 578 579 void stm32mp1_clk_rcc_regs_unlock(void) 580 { 581 stm32mp1_clk_unlock(®_lock); 582 } 583 584 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 585 { 586 if (idx >= NB_OSC) { 587 return 0; 588 } 589 590 return stm32mp1_osc[idx]; 591 } 592 593 static int stm32mp1_clk_get_gated_id(unsigned long id) 594 { 595 unsigned int i; 596 597 for (i = 0U; i < NB_GATES; i++) { 598 if (gate_ref(i)->index == id) { 599 return i; 600 } 601 } 602 603 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 604 605 return -EINVAL; 606 } 607 608 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 609 { 610 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 611 } 612 613 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 614 { 615 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 616 } 617 618 static int stm32mp1_clk_get_parent(unsigned long id) 619 { 620 const struct stm32mp1_clk_sel *sel; 621 uint32_t j, p_sel; 622 int i; 623 enum stm32mp1_parent_id p; 624 enum stm32mp1_parent_sel s; 625 uintptr_t rcc_base = stm32mp_rcc_base(); 626 627 for (j = 0U; j < ARRAY_SIZE(stm32mp1_clks); j++) { 628 if (stm32mp1_clks[j][0] == id) { 629 return (int)stm32mp1_clks[j][1]; 630 } 631 } 632 633 i = stm32mp1_clk_get_gated_id(id); 634 if (i < 0) { 635 panic(); 636 } 637 638 p = stm32mp1_clk_get_fixed_parent(i); 639 if (p < _PARENT_NB) { 640 return (int)p; 641 } 642 643 s = stm32mp1_clk_get_sel(i); 644 if (s == _UNKNOWN_SEL) { 645 return -EINVAL; 646 } 647 if (s >= _PARENT_SEL_NB) { 648 panic(); 649 } 650 651 sel = clk_sel_ref(s); 652 p_sel = (mmio_read_32(rcc_base + sel->offset) & sel->msk) >> sel->src; 653 if (p_sel < sel->nb_parent) { 654 return (int)sel->parent[p_sel]; 655 } 656 657 return -EINVAL; 658 } 659 660 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 661 { 662 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 663 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 664 665 return stm32mp1_clk_get_fixed(pll->refclk[src]); 666 } 667 668 /* 669 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 670 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 671 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 672 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 673 */ 674 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 675 { 676 unsigned long refclk, fvco; 677 uint32_t cfgr1, fracr, divm, divn; 678 uintptr_t rcc_base = stm32mp_rcc_base(); 679 680 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 681 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 682 683 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 684 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 685 686 refclk = stm32mp1_pll_get_fref(pll); 687 688 /* 689 * With FRACV : 690 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 691 * Without FRACV 692 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 693 */ 694 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 695 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 696 RCC_PLLNFRACR_FRACV_SHIFT; 697 unsigned long long numerator, denominator; 698 699 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 700 numerator = refclk * numerator; 701 denominator = ((unsigned long long)divm + 1U) << 13; 702 fvco = (unsigned long)(numerator / denominator); 703 } else { 704 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 705 } 706 707 return fvco; 708 } 709 710 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 711 enum stm32mp1_div_id div_id) 712 { 713 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 714 unsigned long dfout; 715 uint32_t cfgr2, divy; 716 717 if (div_id >= _DIV_NB) { 718 return 0; 719 } 720 721 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 722 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 723 724 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 725 726 return dfout; 727 } 728 729 static unsigned long get_clock_rate(int p) 730 { 731 uint32_t reg, clkdiv; 732 unsigned long clock = 0; 733 uintptr_t rcc_base = stm32mp_rcc_base(); 734 735 switch (p) { 736 case _CK_MPU: 737 /* MPU sub system */ 738 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 739 switch (reg & RCC_SELR_SRC_MASK) { 740 case RCC_MPCKSELR_HSI: 741 clock = stm32mp1_clk_get_fixed(_HSI); 742 break; 743 case RCC_MPCKSELR_HSE: 744 clock = stm32mp1_clk_get_fixed(_HSE); 745 break; 746 case RCC_MPCKSELR_PLL: 747 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 748 break; 749 case RCC_MPCKSELR_PLL_MPUDIV: 750 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 751 752 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 753 clkdiv = reg & RCC_MPUDIV_MASK; 754 if (clkdiv != 0U) { 755 clock /= stm32mp1_mpu_div[clkdiv]; 756 } 757 break; 758 default: 759 break; 760 } 761 break; 762 /* AXI sub system */ 763 case _ACLK: 764 case _HCLK2: 765 case _HCLK6: 766 case _PCLK4: 767 case _PCLK5: 768 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 769 switch (reg & RCC_SELR_SRC_MASK) { 770 case RCC_ASSCKSELR_HSI: 771 clock = stm32mp1_clk_get_fixed(_HSI); 772 break; 773 case RCC_ASSCKSELR_HSE: 774 clock = stm32mp1_clk_get_fixed(_HSE); 775 break; 776 case RCC_ASSCKSELR_PLL: 777 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 778 break; 779 default: 780 break; 781 } 782 783 /* System clock divider */ 784 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 785 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 786 787 switch (p) { 788 case _PCLK4: 789 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 790 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 791 break; 792 case _PCLK5: 793 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 794 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 795 break; 796 default: 797 break; 798 } 799 break; 800 /* MCU sub system */ 801 case _CK_MCU: 802 case _PCLK1: 803 case _PCLK2: 804 case _PCLK3: 805 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 806 switch (reg & RCC_SELR_SRC_MASK) { 807 case RCC_MSSCKSELR_HSI: 808 clock = stm32mp1_clk_get_fixed(_HSI); 809 break; 810 case RCC_MSSCKSELR_HSE: 811 clock = stm32mp1_clk_get_fixed(_HSE); 812 break; 813 case RCC_MSSCKSELR_CSI: 814 clock = stm32mp1_clk_get_fixed(_CSI); 815 break; 816 case RCC_MSSCKSELR_PLL: 817 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 818 break; 819 default: 820 break; 821 } 822 823 /* MCU clock divider */ 824 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 825 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 826 827 switch (p) { 828 case _PCLK1: 829 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 830 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 831 break; 832 case _PCLK2: 833 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 834 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 835 break; 836 case _PCLK3: 837 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 838 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 839 break; 840 case _CK_MCU: 841 default: 842 break; 843 } 844 break; 845 case _CK_PER: 846 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 847 switch (reg & RCC_SELR_SRC_MASK) { 848 case RCC_CPERCKSELR_HSI: 849 clock = stm32mp1_clk_get_fixed(_HSI); 850 break; 851 case RCC_CPERCKSELR_HSE: 852 clock = stm32mp1_clk_get_fixed(_HSE); 853 break; 854 case RCC_CPERCKSELR_CSI: 855 clock = stm32mp1_clk_get_fixed(_CSI); 856 break; 857 default: 858 break; 859 } 860 break; 861 case _HSI: 862 case _HSI_KER: 863 clock = stm32mp1_clk_get_fixed(_HSI); 864 break; 865 case _CSI: 866 case _CSI_KER: 867 clock = stm32mp1_clk_get_fixed(_CSI); 868 break; 869 case _HSE: 870 case _HSE_KER: 871 clock = stm32mp1_clk_get_fixed(_HSE); 872 break; 873 case _HSE_KER_DIV2: 874 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 875 break; 876 case _LSI: 877 clock = stm32mp1_clk_get_fixed(_LSI); 878 break; 879 case _LSE: 880 clock = stm32mp1_clk_get_fixed(_LSE); 881 break; 882 /* PLL */ 883 case _PLL1_P: 884 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 885 break; 886 case _PLL1_Q: 887 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 888 break; 889 case _PLL1_R: 890 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 891 break; 892 case _PLL2_P: 893 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 894 break; 895 case _PLL2_Q: 896 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 897 break; 898 case _PLL2_R: 899 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 900 break; 901 case _PLL3_P: 902 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 903 break; 904 case _PLL3_Q: 905 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 906 break; 907 case _PLL3_R: 908 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 909 break; 910 case _PLL4_P: 911 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 912 break; 913 case _PLL4_Q: 914 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 915 break; 916 case _PLL4_R: 917 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 918 break; 919 /* Other */ 920 case _USB_PHY_48: 921 clock = USB_PHY_48_MHZ; 922 break; 923 default: 924 break; 925 } 926 927 return clock; 928 } 929 930 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 931 { 932 uintptr_t rcc_base = stm32mp_rcc_base(); 933 934 if (gate->set_clr != 0U) { 935 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 936 } else { 937 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 938 } 939 940 VERBOSE("Clock %d has been enabled", gate->index); 941 } 942 943 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 944 { 945 uintptr_t rcc_base = stm32mp_rcc_base(); 946 947 if (gate->set_clr != 0U) { 948 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 949 BIT(gate->bit)); 950 } else { 951 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 952 } 953 954 VERBOSE("Clock %d has been disabled", gate->index); 955 } 956 957 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 958 { 959 uintptr_t rcc_base = stm32mp_rcc_base(); 960 961 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 962 } 963 964 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 965 { 966 int i = stm32mp1_clk_get_gated_id(id); 967 968 if (i < 0) { 969 panic(); 970 } 971 972 return gate_refcounts[i]; 973 } 974 975 void __stm32mp1_clk_enable(unsigned long id, bool secure) 976 { 977 const struct stm32mp1_clk_gate *gate; 978 int i = stm32mp1_clk_get_gated_id(id); 979 unsigned int *refcnt; 980 981 if (i < 0) { 982 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 983 panic(); 984 } 985 986 gate = gate_ref(i); 987 refcnt = &gate_refcounts[i]; 988 989 stm32mp1_clk_lock(&refcount_lock); 990 991 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 992 __clk_enable(gate); 993 } 994 995 stm32mp1_clk_unlock(&refcount_lock); 996 } 997 998 void __stm32mp1_clk_disable(unsigned long id, bool secure) 999 { 1000 const struct stm32mp1_clk_gate *gate; 1001 int i = stm32mp1_clk_get_gated_id(id); 1002 unsigned int *refcnt; 1003 1004 if (i < 0) { 1005 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1006 panic(); 1007 } 1008 1009 gate = gate_ref(i); 1010 refcnt = &gate_refcounts[i]; 1011 1012 stm32mp1_clk_lock(&refcount_lock); 1013 1014 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1015 __clk_disable(gate); 1016 } 1017 1018 stm32mp1_clk_unlock(&refcount_lock); 1019 } 1020 1021 void stm32mp_clk_enable(unsigned long id) 1022 { 1023 __stm32mp1_clk_enable(id, true); 1024 } 1025 1026 void stm32mp_clk_disable(unsigned long id) 1027 { 1028 __stm32mp1_clk_disable(id, true); 1029 } 1030 1031 bool stm32mp_clk_is_enabled(unsigned long id) 1032 { 1033 int i = stm32mp1_clk_get_gated_id(id); 1034 1035 if (i < 0) { 1036 panic(); 1037 } 1038 1039 return __clk_is_enabled(gate_ref(i)); 1040 } 1041 1042 unsigned long stm32mp_clk_get_rate(unsigned long id) 1043 { 1044 int p = stm32mp1_clk_get_parent(id); 1045 1046 if (p < 0) { 1047 return 0; 1048 } 1049 1050 return get_clock_rate(p); 1051 } 1052 1053 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1054 { 1055 uintptr_t address = stm32mp_rcc_base() + offset; 1056 1057 if (enable) { 1058 mmio_setbits_32(address, mask_on); 1059 } else { 1060 mmio_clrbits_32(address, mask_on); 1061 } 1062 } 1063 1064 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1065 { 1066 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1067 uintptr_t address = stm32mp_rcc_base() + offset; 1068 1069 mmio_write_32(address, mask_on); 1070 } 1071 1072 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1073 { 1074 uint64_t timeout; 1075 uint32_t mask_test; 1076 uintptr_t address = stm32mp_rcc_base() + offset; 1077 1078 if (enable) { 1079 mask_test = mask_rdy; 1080 } else { 1081 mask_test = 0; 1082 } 1083 1084 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1085 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1086 if (timeout_elapsed(timeout)) { 1087 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1088 mask_rdy, address, enable, mmio_read_32(address)); 1089 return -ETIMEDOUT; 1090 } 1091 } 1092 1093 return 0; 1094 } 1095 1096 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1097 { 1098 uint32_t value; 1099 uintptr_t rcc_base = stm32mp_rcc_base(); 1100 1101 if (digbyp) { 1102 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1103 } 1104 1105 if (bypass || digbyp) { 1106 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1107 } 1108 1109 /* 1110 * Warning: not recommended to switch directly from "high drive" 1111 * to "medium low drive", and vice-versa. 1112 */ 1113 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1114 RCC_BDCR_LSEDRV_SHIFT; 1115 1116 while (value != lsedrv) { 1117 if (value > lsedrv) { 1118 value--; 1119 } else { 1120 value++; 1121 } 1122 1123 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1124 RCC_BDCR_LSEDRV_MASK, 1125 value << RCC_BDCR_LSEDRV_SHIFT); 1126 } 1127 1128 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1129 } 1130 1131 static void stm32mp1_lse_wait(void) 1132 { 1133 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1134 VERBOSE("%s: failed\n", __func__); 1135 } 1136 } 1137 1138 static void stm32mp1_lsi_set(bool enable) 1139 { 1140 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1141 1142 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1143 VERBOSE("%s: failed\n", __func__); 1144 } 1145 } 1146 1147 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1148 { 1149 uintptr_t rcc_base = stm32mp_rcc_base(); 1150 1151 if (digbyp) { 1152 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1153 } 1154 1155 if (bypass || digbyp) { 1156 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1157 } 1158 1159 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1160 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1161 VERBOSE("%s: failed\n", __func__); 1162 } 1163 1164 if (css) { 1165 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1166 } 1167 } 1168 1169 static void stm32mp1_csi_set(bool enable) 1170 { 1171 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1172 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1173 VERBOSE("%s: failed\n", __func__); 1174 } 1175 } 1176 1177 static void stm32mp1_hsi_set(bool enable) 1178 { 1179 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1180 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1181 VERBOSE("%s: failed\n", __func__); 1182 } 1183 } 1184 1185 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1186 { 1187 uint64_t timeout; 1188 uintptr_t rcc_base = stm32mp_rcc_base(); 1189 uintptr_t address = rcc_base + RCC_OCRDYR; 1190 1191 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1192 RCC_HSICFGR_HSIDIV_MASK, 1193 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1194 1195 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1196 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1197 if (timeout_elapsed(timeout)) { 1198 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1199 address, mmio_read_32(address)); 1200 return -ETIMEDOUT; 1201 } 1202 } 1203 1204 return 0; 1205 } 1206 1207 static int stm32mp1_hsidiv(unsigned long hsifreq) 1208 { 1209 uint8_t hsidiv; 1210 uint32_t hsidivfreq = MAX_HSI_HZ; 1211 1212 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1213 if (hsidivfreq == hsifreq) { 1214 break; 1215 } 1216 1217 hsidivfreq /= 2U; 1218 } 1219 1220 if (hsidiv == 4U) { 1221 ERROR("Invalid clk-hsi frequency\n"); 1222 return -1; 1223 } 1224 1225 if (hsidiv != 0U) { 1226 return stm32mp1_set_hsidiv(hsidiv); 1227 } 1228 1229 return 0; 1230 } 1231 1232 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1233 unsigned int clksrc, 1234 uint32_t *pllcfg, int plloff) 1235 { 1236 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1237 uintptr_t rcc_base = stm32mp_rcc_base(); 1238 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1239 enum stm32mp1_plltype type = pll->plltype; 1240 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1241 unsigned long refclk; 1242 uint32_t ifrge = 0U; 1243 uint32_t src, value, fracv = 0; 1244 void *fdt; 1245 1246 /* Check PLL output */ 1247 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1248 return false; 1249 } 1250 1251 /* Check current clksrc */ 1252 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1253 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1254 return false; 1255 } 1256 1257 /* Check Div */ 1258 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1259 1260 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1261 (pllcfg[PLLCFG_M] + 1U); 1262 1263 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1264 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1265 return false; 1266 } 1267 1268 if ((type == PLL_800) && (refclk >= 8000000U)) { 1269 ifrge = 1U; 1270 } 1271 1272 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1273 RCC_PLLNCFGR1_DIVN_MASK; 1274 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1275 RCC_PLLNCFGR1_DIVM_MASK; 1276 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1277 RCC_PLLNCFGR1_IFRGE_MASK; 1278 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1279 return false; 1280 } 1281 1282 /* Fractional configuration */ 1283 if (fdt_get_address(&fdt) == 1) { 1284 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1285 } 1286 1287 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1288 value |= RCC_PLLNFRACR_FRACLE; 1289 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1290 return false; 1291 } 1292 1293 /* Output config */ 1294 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1295 RCC_PLLNCFGR2_DIVP_MASK; 1296 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1297 RCC_PLLNCFGR2_DIVQ_MASK; 1298 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1299 RCC_PLLNCFGR2_DIVR_MASK; 1300 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1301 return false; 1302 } 1303 1304 return true; 1305 } 1306 1307 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1308 { 1309 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1310 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1311 1312 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1313 mmio_clrsetbits_32(pllxcr, 1314 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1315 RCC_PLLNCR_DIVREN, 1316 RCC_PLLNCR_PLLON); 1317 } 1318 1319 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1320 { 1321 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1322 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1323 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1324 1325 /* Wait PLL lock */ 1326 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1327 if (timeout_elapsed(timeout)) { 1328 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1329 pll_id, pllxcr, mmio_read_32(pllxcr)); 1330 return -ETIMEDOUT; 1331 } 1332 } 1333 1334 /* Start the requested output */ 1335 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1336 1337 return 0; 1338 } 1339 1340 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1341 { 1342 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1343 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1344 uint64_t timeout; 1345 1346 /* Stop all output */ 1347 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1348 RCC_PLLNCR_DIVREN); 1349 1350 /* Stop PLL */ 1351 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1352 1353 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1354 /* Wait PLL stopped */ 1355 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1356 if (timeout_elapsed(timeout)) { 1357 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1358 pll_id, pllxcr, mmio_read_32(pllxcr)); 1359 return -ETIMEDOUT; 1360 } 1361 } 1362 1363 return 0; 1364 } 1365 1366 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1367 uint32_t *pllcfg) 1368 { 1369 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1370 uintptr_t rcc_base = stm32mp_rcc_base(); 1371 uint32_t value; 1372 1373 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1374 RCC_PLLNCFGR2_DIVP_MASK; 1375 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1376 RCC_PLLNCFGR2_DIVQ_MASK; 1377 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1378 RCC_PLLNCFGR2_DIVR_MASK; 1379 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1380 } 1381 1382 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1383 uint32_t *pllcfg, uint32_t fracv) 1384 { 1385 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1386 uintptr_t rcc_base = stm32mp_rcc_base(); 1387 enum stm32mp1_plltype type = pll->plltype; 1388 unsigned long refclk; 1389 uint32_t ifrge = 0; 1390 uint32_t src, value; 1391 1392 src = mmio_read_32(rcc_base + pll->rckxselr) & 1393 RCC_SELR_REFCLK_SRC_MASK; 1394 1395 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1396 (pllcfg[PLLCFG_M] + 1U); 1397 1398 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1399 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1400 return -EINVAL; 1401 } 1402 1403 if ((type == PLL_800) && (refclk >= 8000000U)) { 1404 ifrge = 1U; 1405 } 1406 1407 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1408 RCC_PLLNCFGR1_DIVN_MASK; 1409 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1410 RCC_PLLNCFGR1_DIVM_MASK; 1411 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1412 RCC_PLLNCFGR1_IFRGE_MASK; 1413 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1414 1415 /* Fractional configuration */ 1416 value = 0; 1417 mmio_write_32(rcc_base + pll->pllxfracr, value); 1418 1419 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1420 mmio_write_32(rcc_base + pll->pllxfracr, value); 1421 1422 value |= RCC_PLLNFRACR_FRACLE; 1423 mmio_write_32(rcc_base + pll->pllxfracr, value); 1424 1425 stm32mp1_pll_config_output(pll_id, pllcfg); 1426 1427 return 0; 1428 } 1429 1430 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1431 { 1432 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1433 uint32_t pllxcsg = 0; 1434 1435 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1436 RCC_PLLNCSGR_MOD_PER_MASK; 1437 1438 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1439 RCC_PLLNCSGR_INC_STEP_MASK; 1440 1441 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1442 RCC_PLLNCSGR_SSCG_MODE_MASK; 1443 1444 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1445 1446 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1447 RCC_PLLNCR_SSCG_CTRL); 1448 } 1449 1450 static int stm32mp1_set_clksrc(unsigned int clksrc) 1451 { 1452 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1453 uint64_t timeout; 1454 1455 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1456 clksrc & RCC_SELR_SRC_MASK); 1457 1458 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1459 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1460 if (timeout_elapsed(timeout)) { 1461 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1462 clksrc_address, mmio_read_32(clksrc_address)); 1463 return -ETIMEDOUT; 1464 } 1465 } 1466 1467 return 0; 1468 } 1469 1470 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1471 { 1472 uint64_t timeout; 1473 1474 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1475 clkdiv & RCC_DIVR_DIV_MASK); 1476 1477 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1478 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1479 if (timeout_elapsed(timeout)) { 1480 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1481 clkdiv, address, mmio_read_32(address)); 1482 return -ETIMEDOUT; 1483 } 1484 } 1485 1486 return 0; 1487 } 1488 1489 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1490 { 1491 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1492 1493 /* 1494 * Binding clksrc : 1495 * bit15-4 offset 1496 * bit3: disable 1497 * bit2-0: MCOSEL[2:0] 1498 */ 1499 if ((clksrc & 0x8U) != 0U) { 1500 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1501 } else { 1502 mmio_clrsetbits_32(clksrc_address, 1503 RCC_MCOCFG_MCOSRC_MASK, 1504 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1505 mmio_clrsetbits_32(clksrc_address, 1506 RCC_MCOCFG_MCODIV_MASK, 1507 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1508 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1509 } 1510 } 1511 1512 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1513 { 1514 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1515 1516 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1517 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1518 mmio_clrsetbits_32(address, 1519 RCC_BDCR_RTCSRC_MASK, 1520 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1521 1522 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1523 } 1524 1525 if (lse_css) { 1526 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1527 } 1528 } 1529 1530 static void stm32mp1_stgen_config(void) 1531 { 1532 uintptr_t stgen; 1533 uint32_t cntfid0; 1534 unsigned long rate; 1535 unsigned long long counter; 1536 1537 stgen = fdt_get_stgen_base(); 1538 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1539 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1540 1541 if (cntfid0 == rate) { 1542 return; 1543 } 1544 1545 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1546 counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); 1547 counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; 1548 counter = (counter * rate / cntfid0); 1549 1550 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1551 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1552 mmio_write_32(stgen + CNTFID_OFF, rate); 1553 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1554 1555 write_cntfrq((u_register_t)rate); 1556 1557 /* Need to update timer with new frequency */ 1558 generic_delay_timer_init(); 1559 } 1560 1561 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1562 { 1563 uintptr_t stgen; 1564 unsigned long long cnt; 1565 1566 stgen = fdt_get_stgen_base(); 1567 1568 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1569 mmio_read_32(stgen + CNTCVL_OFF); 1570 1571 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1572 1573 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1574 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1575 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1576 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1577 } 1578 1579 static void stm32mp1_pkcs_config(uint32_t pkcs) 1580 { 1581 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1582 uint32_t value = pkcs & 0xFU; 1583 uint32_t mask = 0xFU; 1584 1585 if ((pkcs & BIT(31)) != 0U) { 1586 mask <<= 4; 1587 value <<= 4; 1588 } 1589 1590 mmio_clrsetbits_32(address, mask, value); 1591 } 1592 1593 int stm32mp1_clk_init(void) 1594 { 1595 uintptr_t rcc_base = stm32mp_rcc_base(); 1596 unsigned int clksrc[CLKSRC_NB]; 1597 unsigned int clkdiv[CLKDIV_NB]; 1598 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1599 int plloff[_PLL_NB]; 1600 int ret, len; 1601 enum stm32mp1_pll_id i; 1602 bool lse_css = false; 1603 bool pll3_preserve = false; 1604 bool pll4_preserve = false; 1605 bool pll4_bootrom = false; 1606 const fdt32_t *pkcs_cell; 1607 void *fdt; 1608 1609 if (fdt_get_address(&fdt) == 0) { 1610 return false; 1611 } 1612 1613 /* Check status field to disable security */ 1614 if (!fdt_get_rcc_secure_status()) { 1615 mmio_write_32(rcc_base + RCC_TZCR, 0); 1616 } 1617 1618 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1619 clksrc); 1620 if (ret < 0) { 1621 return -FDT_ERR_NOTFOUND; 1622 } 1623 1624 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1625 clkdiv); 1626 if (ret < 0) { 1627 return -FDT_ERR_NOTFOUND; 1628 } 1629 1630 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1631 char name[12]; 1632 1633 snprintf(name, sizeof(name), "st,pll@%d", i); 1634 plloff[i] = fdt_rcc_subnode_offset(name); 1635 1636 if (!fdt_check_node(plloff[i])) { 1637 continue; 1638 } 1639 1640 ret = fdt_read_uint32_array(fdt, plloff[i], "cfg", 1641 (int)PLLCFG_NB, pllcfg[i]); 1642 if (ret < 0) { 1643 return -FDT_ERR_NOTFOUND; 1644 } 1645 } 1646 1647 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1648 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1649 1650 /* 1651 * Switch ON oscillator found in device-tree. 1652 * Note: HSI already ON after BootROM stage. 1653 */ 1654 if (stm32mp1_osc[_LSI] != 0U) { 1655 stm32mp1_lsi_set(true); 1656 } 1657 if (stm32mp1_osc[_LSE] != 0U) { 1658 bool bypass, digbyp; 1659 uint32_t lsedrv; 1660 1661 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1662 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1663 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1664 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1665 LSEDRV_MEDIUM_HIGH); 1666 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1667 } 1668 if (stm32mp1_osc[_HSE] != 0U) { 1669 bool bypass, digbyp, css; 1670 1671 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1672 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1673 css = fdt_osc_read_bool(_HSE, "st,css"); 1674 stm32mp1_hse_enable(bypass, digbyp, css); 1675 } 1676 /* 1677 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1678 * => switch on CSI even if node is not present in device tree 1679 */ 1680 stm32mp1_csi_set(true); 1681 1682 /* Come back to HSI */ 1683 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1684 if (ret != 0) { 1685 return ret; 1686 } 1687 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1688 if (ret != 0) { 1689 return ret; 1690 } 1691 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1692 if (ret != 0) { 1693 return ret; 1694 } 1695 1696 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1697 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1698 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1699 clksrc[CLKSRC_PLL3], 1700 pllcfg[_PLL3], 1701 plloff[_PLL3]); 1702 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1703 clksrc[CLKSRC_PLL4], 1704 pllcfg[_PLL4], 1705 plloff[_PLL4]); 1706 } 1707 1708 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1709 if (((i == _PLL3) && pll3_preserve) || 1710 ((i == _PLL4) && pll4_preserve)) { 1711 continue; 1712 } 1713 1714 ret = stm32mp1_pll_stop(i); 1715 if (ret != 0) { 1716 return ret; 1717 } 1718 } 1719 1720 /* Configure HSIDIV */ 1721 if (stm32mp1_osc[_HSI] != 0U) { 1722 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1723 if (ret != 0) { 1724 return ret; 1725 } 1726 stm32mp1_stgen_config(); 1727 } 1728 1729 /* Select DIV */ 1730 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1731 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1732 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1733 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1734 if (ret != 0) { 1735 return ret; 1736 } 1737 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1738 if (ret != 0) { 1739 return ret; 1740 } 1741 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1742 if (ret != 0) { 1743 return ret; 1744 } 1745 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1746 if (ret != 0) { 1747 return ret; 1748 } 1749 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1750 if (ret != 0) { 1751 return ret; 1752 } 1753 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1754 if (ret != 0) { 1755 return ret; 1756 } 1757 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1758 if (ret != 0) { 1759 return ret; 1760 } 1761 1762 /* No ready bit for RTC */ 1763 mmio_write_32(rcc_base + RCC_RTCDIVR, 1764 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1765 1766 /* Configure PLLs source */ 1767 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1768 if (ret != 0) { 1769 return ret; 1770 } 1771 1772 if (!pll3_preserve) { 1773 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1774 if (ret != 0) { 1775 return ret; 1776 } 1777 } 1778 1779 if (!pll4_preserve) { 1780 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1781 if (ret != 0) { 1782 return ret; 1783 } 1784 } 1785 1786 /* Configure and start PLLs */ 1787 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1788 uint32_t fracv; 1789 uint32_t csg[PLLCSG_NB]; 1790 1791 if (((i == _PLL3) && pll3_preserve) || 1792 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1793 continue; 1794 } 1795 1796 if (!fdt_check_node(plloff[i])) { 1797 continue; 1798 } 1799 1800 if ((i == _PLL4) && pll4_bootrom) { 1801 /* Set output divider if not done by the Bootrom */ 1802 stm32mp1_pll_config_output(i, pllcfg[i]); 1803 continue; 1804 } 1805 1806 fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0); 1807 1808 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 1809 if (ret != 0) { 1810 return ret; 1811 } 1812 ret = fdt_read_uint32_array(fdt, plloff[i], "csg", 1813 (uint32_t)PLLCSG_NB, csg); 1814 if (ret == 0) { 1815 stm32mp1_pll_csg(i, csg); 1816 } else if (ret != -FDT_ERR_NOTFOUND) { 1817 return ret; 1818 } 1819 1820 stm32mp1_pll_start(i); 1821 } 1822 /* Wait and start PLLs ouptut when ready */ 1823 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1824 if (!fdt_check_node(plloff[i])) { 1825 continue; 1826 } 1827 1828 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 1829 if (ret != 0) { 1830 return ret; 1831 } 1832 } 1833 /* Wait LSE ready before to use it */ 1834 if (stm32mp1_osc[_LSE] != 0U) { 1835 stm32mp1_lse_wait(); 1836 } 1837 1838 /* Configure with expected clock source */ 1839 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 1840 if (ret != 0) { 1841 return ret; 1842 } 1843 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 1844 if (ret != 0) { 1845 return ret; 1846 } 1847 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 1848 if (ret != 0) { 1849 return ret; 1850 } 1851 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 1852 1853 /* Configure PKCK */ 1854 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1855 if (pkcs_cell != NULL) { 1856 bool ckper_disabled = false; 1857 uint32_t j; 1858 1859 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1860 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1861 1862 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1863 ckper_disabled = true; 1864 continue; 1865 } 1866 stm32mp1_pkcs_config(pkcs); 1867 } 1868 1869 /* 1870 * CKPER is source for some peripheral clocks 1871 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1872 * only if previous clock is still ON 1873 * => deactivated CKPER only after switching clock 1874 */ 1875 if (ckper_disabled) { 1876 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 1877 } 1878 } 1879 1880 /* Switch OFF HSI if not found in device-tree */ 1881 if (stm32mp1_osc[_HSI] == 0U) { 1882 stm32mp1_hsi_set(false); 1883 } 1884 stm32mp1_stgen_config(); 1885 1886 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1887 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 1888 RCC_DDRITFCR_DDRCKMOD_MASK, 1889 RCC_DDRITFCR_DDRCKMOD_SSR << 1890 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1891 1892 return 0; 1893 } 1894 1895 static void stm32mp1_osc_clk_init(const char *name, 1896 enum stm32mp_osc_id index) 1897 { 1898 uint32_t frequency; 1899 1900 if (fdt_osc_read_freq(name, &frequency) == 0) { 1901 stm32mp1_osc[index] = frequency; 1902 } 1903 } 1904 1905 static void stm32mp1_osc_init(void) 1906 { 1907 enum stm32mp_osc_id i; 1908 1909 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 1910 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 1911 } 1912 } 1913 1914 static void sync_earlyboot_clocks_state(void) 1915 { 1916 if (!stm32mp_is_single_core()) { 1917 stm32mp1_clk_enable_secure(RTCAPB); 1918 } 1919 } 1920 1921 int stm32mp1_clk_probe(void) 1922 { 1923 stm32mp1_osc_init(); 1924 1925 sync_earlyboot_clocks_state(); 1926 1927 return 0; 1928 } 1929