1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/clock/stm32mp1-clksrc.h> 14 #include <errno.h> 15 #include <generic_delay_timer.h> 16 #include <libfdt.h> 17 #include <mmio.h> 18 #include <platform.h> 19 #include <stdint.h> 20 #include <stm32mp1_clk.h> 21 #include <stm32mp1_clkfunc.h> 22 #include <stm32mp1_dt.h> 23 #include <stm32mp1_private.h> 24 #include <stm32mp1_rcc.h> 25 #include <utils_def.h> 26 27 #define MAX_HSI_HZ 64000000 28 29 #define TIMEOUT_200MS (plat_get_syscnt_freq2() / 5U) 30 #define TIMEOUT_1S plat_get_syscnt_freq2() 31 32 #define PLLRDY_TIMEOUT TIMEOUT_200MS 33 #define CLKSRC_TIMEOUT TIMEOUT_200MS 34 #define CLKDIV_TIMEOUT TIMEOUT_200MS 35 #define HSIDIV_TIMEOUT TIMEOUT_200MS 36 #define OSCRDY_TIMEOUT TIMEOUT_1S 37 38 enum stm32mp1_parent_id { 39 /* Oscillators are defined in enum stm32mp_osc_id */ 40 41 /* Other parent source */ 42 _HSI_KER = NB_OSC, 43 _HSE_KER, 44 _HSE_KER_DIV2, 45 _CSI_KER, 46 _PLL1_P, 47 _PLL1_Q, 48 _PLL1_R, 49 _PLL2_P, 50 _PLL2_Q, 51 _PLL2_R, 52 _PLL3_P, 53 _PLL3_Q, 54 _PLL3_R, 55 _PLL4_P, 56 _PLL4_Q, 57 _PLL4_R, 58 _ACLK, 59 _PCLK1, 60 _PCLK2, 61 _PCLK3, 62 _PCLK4, 63 _PCLK5, 64 _HCLK6, 65 _HCLK2, 66 _CK_PER, 67 _CK_MPU, 68 _PARENT_NB, 69 _UNKNOWN_ID = 0xff, 70 }; 71 72 enum stm32mp1_parent_sel { 73 _I2C46_SEL, 74 _UART6_SEL, 75 _UART24_SEL, 76 _UART35_SEL, 77 _UART78_SEL, 78 _SDMMC12_SEL, 79 _SDMMC3_SEL, 80 _QSPI_SEL, 81 _FMC_SEL, 82 _USBPHY_SEL, 83 _USBO_SEL, 84 _STGEN_SEL, 85 _PARENT_SEL_NB, 86 _UNKNOWN_SEL = 0xff, 87 }; 88 89 enum stm32mp1_pll_id { 90 _PLL1, 91 _PLL2, 92 _PLL3, 93 _PLL4, 94 _PLL_NB 95 }; 96 97 enum stm32mp1_div_id { 98 _DIV_P, 99 _DIV_Q, 100 _DIV_R, 101 _DIV_NB, 102 }; 103 104 enum stm32mp1_clksrc_id { 105 CLKSRC_MPU, 106 CLKSRC_AXI, 107 CLKSRC_PLL12, 108 CLKSRC_PLL3, 109 CLKSRC_PLL4, 110 CLKSRC_RTC, 111 CLKSRC_MCO1, 112 CLKSRC_MCO2, 113 CLKSRC_NB 114 }; 115 116 enum stm32mp1_clkdiv_id { 117 CLKDIV_MPU, 118 CLKDIV_AXI, 119 CLKDIV_APB1, 120 CLKDIV_APB2, 121 CLKDIV_APB3, 122 CLKDIV_APB4, 123 CLKDIV_APB5, 124 CLKDIV_RTC, 125 CLKDIV_MCO1, 126 CLKDIV_MCO2, 127 CLKDIV_NB 128 }; 129 130 enum stm32mp1_pllcfg { 131 PLLCFG_M, 132 PLLCFG_N, 133 PLLCFG_P, 134 PLLCFG_Q, 135 PLLCFG_R, 136 PLLCFG_O, 137 PLLCFG_NB 138 }; 139 140 enum stm32mp1_pllcsg { 141 PLLCSG_MOD_PER, 142 PLLCSG_INC_STEP, 143 PLLCSG_SSCG_MODE, 144 PLLCSG_NB 145 }; 146 147 enum stm32mp1_plltype { 148 PLL_800, 149 PLL_1600, 150 PLL_TYPE_NB 151 }; 152 153 struct stm32mp1_pll { 154 uint8_t refclk_min; 155 uint8_t refclk_max; 156 uint8_t divn_max; 157 }; 158 159 struct stm32mp1_clk_gate { 160 uint16_t offset; 161 uint8_t bit; 162 uint8_t index; 163 uint8_t set_clr; 164 enum stm32mp1_parent_sel sel; 165 enum stm32mp1_parent_id fixed; 166 bool secure; 167 }; 168 169 struct stm32mp1_clk_sel { 170 uint16_t offset; 171 uint8_t src; 172 uint8_t msk; 173 uint8_t nb_parent; 174 const uint8_t *parent; 175 }; 176 177 #define REFCLK_SIZE 4 178 struct stm32mp1_clk_pll { 179 enum stm32mp1_plltype plltype; 180 uint16_t rckxselr; 181 uint16_t pllxcfgr1; 182 uint16_t pllxcfgr2; 183 uint16_t pllxfracr; 184 uint16_t pllxcr; 185 uint16_t pllxcsgr; 186 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 187 }; 188 189 struct stm32mp1_clk_data { 190 const struct stm32mp1_clk_gate *gate; 191 const struct stm32mp1_clk_sel *sel; 192 const struct stm32mp1_clk_pll *pll; 193 const int nb_gate; 194 }; 195 196 struct stm32mp1_clk_priv { 197 uint32_t base; 198 const struct stm32mp1_clk_data *data; 199 unsigned long osc[NB_OSC]; 200 uint32_t pkcs_usb_value; 201 }; 202 203 #define STM32MP1_CLK(off, b, idx, s) \ 204 { \ 205 .offset = (off), \ 206 .bit = (b), \ 207 .index = (idx), \ 208 .set_clr = 0, \ 209 .sel = (s), \ 210 .fixed = _UNKNOWN_ID, \ 211 .secure = 0, \ 212 } 213 214 #define STM32MP1_CLK_F(off, b, idx, f) \ 215 { \ 216 .offset = (off), \ 217 .bit = (b), \ 218 .index = (idx), \ 219 .set_clr = 0, \ 220 .sel = _UNKNOWN_SEL, \ 221 .fixed = (f), \ 222 .secure = 0, \ 223 } 224 225 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ 226 { \ 227 .offset = (off), \ 228 .bit = (b), \ 229 .index = (idx), \ 230 .set_clr = 1, \ 231 .sel = (s), \ 232 .fixed = _UNKNOWN_ID, \ 233 .secure = 0, \ 234 } 235 236 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ 237 { \ 238 .offset = (off), \ 239 .bit = (b), \ 240 .index = (idx), \ 241 .set_clr = 1, \ 242 .sel = _UNKNOWN_SEL, \ 243 .fixed = (f), \ 244 .secure = 0, \ 245 } 246 247 #define STM32MP1_CLK_SEC_SET_CLR(off, b, idx, s) \ 248 { \ 249 .offset = (off), \ 250 .bit = (b), \ 251 .index = (idx), \ 252 .set_clr = 1, \ 253 .sel = (s), \ 254 .fixed = _UNKNOWN_ID, \ 255 .secure = 1, \ 256 } 257 258 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ 259 [(idx)] = { \ 260 .offset = (off), \ 261 .src = (s), \ 262 .msk = (m), \ 263 .parent = (p), \ 264 .nb_parent = ARRAY_SIZE((p)) \ 265 } 266 267 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, \ 268 off4, off5, off6, \ 269 p1, p2, p3, p4) \ 270 [(idx)] = { \ 271 .plltype = (type), \ 272 .rckxselr = (off1), \ 273 .pllxcfgr1 = (off2), \ 274 .pllxcfgr2 = (off3), \ 275 .pllxfracr = (off4), \ 276 .pllxcr = (off5), \ 277 .pllxcsgr = (off6), \ 278 .refclk[0] = (p1), \ 279 .refclk[1] = (p2), \ 280 .refclk[2] = (p3), \ 281 .refclk[3] = (p4), \ 282 } 283 284 static const uint8_t stm32mp1_clks[][2] = { 285 {CK_PER, _CK_PER}, 286 {CK_MPU, _CK_MPU}, 287 {CK_AXI, _ACLK}, 288 {CK_HSE, _HSE}, 289 {CK_CSI, _CSI}, 290 {CK_LSI, _LSI}, 291 {CK_LSE, _LSE}, 292 {CK_HSI, _HSI}, 293 {CK_HSE_DIV2, _HSE_KER_DIV2}, 294 }; 295 296 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 297 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), 298 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), 299 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), 300 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), 301 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 302 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), 303 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), 304 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), 305 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), 306 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), 307 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), 308 309 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 310 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 311 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 312 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 313 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 314 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 315 316 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 317 318 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 319 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 320 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 321 322 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 323 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 324 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 11, TZC1, _UNKNOWN_SEL), 325 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 12, TZC2, _UNKNOWN_SEL), 326 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 327 328 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 329 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 330 331 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 332 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 333 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 334 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 335 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 336 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 337 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 338 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 339 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 340 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 341 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 342 343 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), 344 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 5, HASH1, _UNKNOWN_SEL), 345 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _CSI_KER), 346 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _UNKNOWN_SEL), 347 348 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 349 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 350 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 351 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 352 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 353 354 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 355 }; 356 357 static const uint8_t i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; 358 static const uint8_t uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, 359 _HSE_KER}; 360 static const uint8_t uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 361 _HSE_KER}; 362 static const uint8_t uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 363 _HSE_KER}; 364 static const uint8_t uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 365 _HSE_KER}; 366 static const uint8_t sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; 367 static const uint8_t sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; 368 static const uint8_t qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 369 static const uint8_t fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 370 static const uint8_t usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; 371 static const uint8_t usbo_parents[] = {_PLL4_R, _USB_PHY_48}; 372 static const uint8_t stgen_parents[] = {_HSI_KER, _HSE_KER}; 373 374 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 375 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 376 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 377 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, 378 uart24_parents), 379 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, 380 uart35_parents), 381 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, 382 uart78_parents), 383 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, 384 sdmmc12_parents), 385 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, 386 sdmmc3_parents), 387 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), 388 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), 389 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), 390 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), 391 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 392 }; 393 394 /* Define characteristic of PLL according type */ 395 #define DIVN_MIN 24 396 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 397 [PLL_800] = { 398 .refclk_min = 4, 399 .refclk_max = 16, 400 .divn_max = 99, 401 }, 402 [PLL_1600] = { 403 .refclk_min = 8, 404 .refclk_max = 16, 405 .divn_max = 199, 406 }, 407 }; 408 409 /* PLLNCFGR2 register divider by output */ 410 static const uint8_t pllncfgr2[_DIV_NB] = { 411 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 412 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 413 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT 414 }; 415 416 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 417 STM32MP1_CLK_PLL(_PLL1, PLL_1600, 418 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 419 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 420 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 421 STM32MP1_CLK_PLL(_PLL2, PLL_1600, 422 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 423 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 424 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 425 STM32MP1_CLK_PLL(_PLL3, PLL_800, 426 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 427 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 428 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 429 STM32MP1_CLK_PLL(_PLL4, PLL_800, 430 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 431 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 432 _HSI, _HSE, _CSI, _I2S_CKIN), 433 }; 434 435 /* Prescaler table lookups for clock computation */ 436 437 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 438 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 439 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 440 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 441 0, 1, 2, 3, 4, 4, 4, 4 442 }; 443 444 /* div = /1 /2 /3 /4 */ 445 static const uint8_t stm32mp1_axi_div[8] = { 446 1, 2, 3, 4, 4, 4, 4, 4 447 }; 448 449 static const struct stm32mp1_clk_data stm32mp1_data = { 450 .gate = stm32mp1_clk_gate, 451 .sel = stm32mp1_clk_sel, 452 .pll = stm32mp1_clk_pll, 453 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), 454 }; 455 456 static struct stm32mp1_clk_priv stm32mp1_clk_priv_data; 457 458 static unsigned long stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, 459 enum stm32mp_osc_id idx) 460 { 461 if (idx >= NB_OSC) { 462 return 0; 463 } 464 465 return priv->osc[idx]; 466 } 467 468 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) 469 { 470 const struct stm32mp1_clk_gate *gate = priv->data->gate; 471 int i; 472 int nb_clks = priv->data->nb_gate; 473 474 for (i = 0; i < nb_clks; i++) { 475 if (gate[i].index == id) { 476 return i; 477 } 478 } 479 480 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 481 482 return -EINVAL; 483 } 484 485 static enum stm32mp1_parent_sel 486 stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, int i) 487 { 488 const struct stm32mp1_clk_gate *gate = priv->data->gate; 489 490 return gate[i].sel; 491 } 492 493 static enum stm32mp1_parent_id 494 stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, int i) 495 { 496 const struct stm32mp1_clk_gate *gate = priv->data->gate; 497 498 return gate[i].fixed; 499 } 500 501 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, 502 unsigned long id) 503 { 504 const struct stm32mp1_clk_sel *sel = priv->data->sel; 505 uint32_t j, p_sel; 506 int i; 507 enum stm32mp1_parent_id p; 508 enum stm32mp1_parent_sel s; 509 510 for (j = 0; j < ARRAY_SIZE(stm32mp1_clks); j++) { 511 if (stm32mp1_clks[j][0] == id) { 512 return (int)stm32mp1_clks[j][1]; 513 } 514 } 515 516 i = stm32mp1_clk_get_id(priv, id); 517 if (i < 0) { 518 return i; 519 } 520 521 p = stm32mp1_clk_get_fixed_parent(priv, i); 522 if (p < _PARENT_NB) { 523 return (int)p; 524 } 525 526 s = stm32mp1_clk_get_sel(priv, i); 527 if (s >= _PARENT_SEL_NB) { 528 return -EINVAL; 529 } 530 531 p_sel = (mmio_read_32(priv->base + sel[s].offset) >> sel[s].src) & 532 sel[s].msk; 533 534 if (p_sel < sel[s].nb_parent) { 535 return (int)sel[s].parent[p_sel]; 536 } 537 538 ERROR("%s: no parents defined for clk id %ld\n", __func__, id); 539 540 return -EINVAL; 541 } 542 543 static unsigned long stm32mp1_pll_get_fref_ck(struct stm32mp1_clk_priv *priv, 544 enum stm32mp1_pll_id pll_id) 545 { 546 const struct stm32mp1_clk_pll *pll = priv->data->pll; 547 uint32_t selr, src; 548 unsigned long refclk; 549 550 selr = mmio_read_32(priv->base + pll[pll_id].rckxselr); 551 src = selr & RCC_SELR_REFCLK_SRC_MASK; 552 553 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); 554 555 return refclk; 556 } 557 558 /* 559 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 560 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 561 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 562 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 563 */ 564 static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv, 565 enum stm32mp1_pll_id pll_id) 566 { 567 const struct stm32mp1_clk_pll *pll = priv->data->pll; 568 unsigned long refclk, fvco; 569 uint32_t cfgr1, fracr, divm, divn; 570 571 cfgr1 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr1); 572 fracr = mmio_read_32(priv->base + pll[pll_id].pllxfracr); 573 574 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 575 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 576 577 refclk = stm32mp1_pll_get_fref_ck(priv, pll_id); 578 579 /* 580 * With FRACV : 581 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 582 * Without FRACV 583 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 584 */ 585 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 586 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) 587 >> RCC_PLLNFRACR_FRACV_SHIFT; 588 unsigned long long numerator, denominator; 589 590 numerator = ((unsigned long long)divn + 1U) << 13; 591 numerator = (refclk * numerator) + fracv; 592 denominator = ((unsigned long long)divm + 1U) << 13; 593 fvco = (unsigned long)(numerator / denominator); 594 } else { 595 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 596 } 597 598 return fvco; 599 } 600 601 static unsigned long stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, 602 enum stm32mp1_pll_id pll_id, 603 enum stm32mp1_div_id div_id) 604 { 605 const struct stm32mp1_clk_pll *pll = priv->data->pll; 606 unsigned long dfout; 607 uint32_t cfgr2, divy; 608 609 if (div_id >= _DIV_NB) { 610 return 0; 611 } 612 613 cfgr2 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr2); 614 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 615 616 dfout = stm32mp1_pll_get_fvco(priv, pll_id) / (divy + 1U); 617 618 return dfout; 619 } 620 621 static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) 622 { 623 uint32_t reg, clkdiv; 624 unsigned long clock = 0; 625 626 switch (p) { 627 case _CK_MPU: 628 /* MPU sub system */ 629 reg = mmio_read_32(priv->base + RCC_MPCKSELR); 630 switch (reg & RCC_SELR_SRC_MASK) { 631 case RCC_MPCKSELR_HSI: 632 clock = stm32mp1_clk_get_fixed(priv, _HSI); 633 break; 634 case RCC_MPCKSELR_HSE: 635 clock = stm32mp1_clk_get_fixed(priv, _HSE); 636 break; 637 case RCC_MPCKSELR_PLL: 638 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 639 break; 640 case RCC_MPCKSELR_PLL_MPUDIV: 641 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 642 643 reg = mmio_read_32(priv->base + RCC_MPCKDIVR); 644 clkdiv = reg & RCC_MPUDIV_MASK; 645 if (clkdiv != 0U) { 646 clock /= stm32mp1_mpu_div[clkdiv]; 647 } 648 649 break; 650 default: 651 break; 652 } 653 break; 654 /* AXI sub system */ 655 case _ACLK: 656 case _HCLK2: 657 case _HCLK6: 658 case _PCLK4: 659 case _PCLK5: 660 reg = mmio_read_32(priv->base + RCC_ASSCKSELR); 661 switch (reg & RCC_SELR_SRC_MASK) { 662 case RCC_ASSCKSELR_HSI: 663 clock = stm32mp1_clk_get_fixed(priv, _HSI); 664 break; 665 case RCC_ASSCKSELR_HSE: 666 clock = stm32mp1_clk_get_fixed(priv, _HSE); 667 break; 668 case RCC_ASSCKSELR_PLL: 669 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 670 break; 671 default: 672 break; 673 } 674 675 /* System clock divider */ 676 reg = mmio_read_32(priv->base + RCC_AXIDIVR); 677 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 678 679 switch (p) { 680 case _PCLK4: 681 reg = mmio_read_32(priv->base + RCC_APB4DIVR); 682 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 683 break; 684 case _PCLK5: 685 reg = mmio_read_32(priv->base + RCC_APB5DIVR); 686 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 687 break; 688 default: 689 break; 690 } 691 break; 692 case _CK_PER: 693 reg = mmio_read_32(priv->base + RCC_CPERCKSELR); 694 switch (reg & RCC_SELR_SRC_MASK) { 695 case RCC_CPERCKSELR_HSI: 696 clock = stm32mp1_clk_get_fixed(priv, _HSI); 697 break; 698 case RCC_CPERCKSELR_HSE: 699 clock = stm32mp1_clk_get_fixed(priv, _HSE); 700 break; 701 case RCC_CPERCKSELR_CSI: 702 clock = stm32mp1_clk_get_fixed(priv, _CSI); 703 break; 704 default: 705 break; 706 } 707 break; 708 case _HSI: 709 case _HSI_KER: 710 clock = stm32mp1_clk_get_fixed(priv, _HSI); 711 break; 712 case _CSI: 713 case _CSI_KER: 714 clock = stm32mp1_clk_get_fixed(priv, _CSI); 715 break; 716 case _HSE: 717 case _HSE_KER: 718 clock = stm32mp1_clk_get_fixed(priv, _HSE); 719 break; 720 case _HSE_KER_DIV2: 721 clock = stm32mp1_clk_get_fixed(priv, _HSE) >> 1; 722 break; 723 case _LSI: 724 clock = stm32mp1_clk_get_fixed(priv, _LSI); 725 break; 726 case _LSE: 727 clock = stm32mp1_clk_get_fixed(priv, _LSE); 728 break; 729 /* PLL */ 730 case _PLL1_P: 731 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 732 break; 733 case _PLL1_Q: 734 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_Q); 735 break; 736 case _PLL1_R: 737 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_R); 738 break; 739 case _PLL2_P: 740 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 741 break; 742 case _PLL2_Q: 743 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_Q); 744 break; 745 case _PLL2_R: 746 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_R); 747 break; 748 case _PLL3_P: 749 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); 750 break; 751 case _PLL3_Q: 752 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_Q); 753 break; 754 case _PLL3_R: 755 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_R); 756 break; 757 case _PLL4_P: 758 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_P); 759 break; 760 case _PLL4_Q: 761 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_Q); 762 break; 763 case _PLL4_R: 764 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_R); 765 break; 766 /* Other */ 767 case _USB_PHY_48: 768 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); 769 break; 770 default: 771 break; 772 } 773 774 return clock; 775 } 776 777 bool stm32mp1_clk_is_enabled(unsigned long id) 778 { 779 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 780 const struct stm32mp1_clk_gate *gate = priv->data->gate; 781 int i = stm32mp1_clk_get_id(priv, id); 782 783 if (i < 0) { 784 return false; 785 } 786 787 return ((mmio_read_32(priv->base + gate[i].offset) & 788 BIT(gate[i].bit)) != 0U); 789 } 790 791 int stm32mp1_clk_enable(unsigned long id) 792 { 793 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 794 const struct stm32mp1_clk_gate *gate = priv->data->gate; 795 int i = stm32mp1_clk_get_id(priv, id); 796 797 if (i < 0) { 798 return i; 799 } 800 801 if (gate[i].set_clr != 0U) { 802 mmio_write_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 803 } else { 804 mmio_setbits_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 805 } 806 807 return 0; 808 } 809 810 int stm32mp1_clk_disable(unsigned long id) 811 { 812 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 813 const struct stm32mp1_clk_gate *gate = priv->data->gate; 814 int i = stm32mp1_clk_get_id(priv, id); 815 816 if (i < 0) { 817 return i; 818 } 819 820 if (gate[i].set_clr != 0U) { 821 mmio_write_32(priv->base + gate[i].offset 822 + RCC_MP_ENCLRR_OFFSET, 823 BIT(gate[i].bit)); 824 } else { 825 mmio_clrbits_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 826 } 827 828 return 0; 829 } 830 831 unsigned long stm32mp1_clk_get_rate(unsigned long id) 832 { 833 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 834 int p = stm32mp1_clk_get_parent(priv, id); 835 unsigned long rate; 836 837 if (p < 0) { 838 return 0; 839 } 840 841 rate = stm32mp1_clk_get(priv, p); 842 843 return rate; 844 } 845 846 static void stm32mp1_ls_osc_set(int enable, uint32_t rcc, uint32_t offset, 847 uint32_t mask_on) 848 { 849 uint32_t address = rcc + offset; 850 851 if (enable != 0) { 852 mmio_setbits_32(address, mask_on); 853 } else { 854 mmio_clrbits_32(address, mask_on); 855 } 856 } 857 858 static void stm32mp1_hs_ocs_set(int enable, uint32_t rcc, uint32_t mask_on) 859 { 860 if (enable != 0) { 861 mmio_setbits_32(rcc + RCC_OCENSETR, mask_on); 862 } else { 863 mmio_setbits_32(rcc + RCC_OCENCLRR, mask_on); 864 } 865 } 866 867 static int stm32mp1_osc_wait(int enable, uint32_t rcc, uint32_t offset, 868 uint32_t mask_rdy) 869 { 870 unsigned long start; 871 uint32_t mask_test; 872 uint32_t address = rcc + offset; 873 874 if (enable != 0) { 875 mask_test = mask_rdy; 876 } else { 877 mask_test = 0; 878 } 879 880 start = get_timer(0); 881 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 882 if (get_timer(start) > OSCRDY_TIMEOUT) { 883 ERROR("OSC %x @ %x timeout for enable=%d : 0x%x\n", 884 mask_rdy, address, enable, mmio_read_32(address)); 885 return -ETIMEDOUT; 886 } 887 } 888 889 return 0; 890 } 891 892 static void stm32mp1_lse_enable(uint32_t rcc, bool bypass, uint32_t lsedrv) 893 { 894 uint32_t value; 895 896 if (bypass) { 897 mmio_setbits_32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); 898 } 899 900 /* 901 * Warning: not recommended to switch directly from "high drive" 902 * to "medium low drive", and vice-versa. 903 */ 904 value = (mmio_read_32(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 905 RCC_BDCR_LSEDRV_SHIFT; 906 907 while (value != lsedrv) { 908 if (value > lsedrv) { 909 value--; 910 } else { 911 value++; 912 } 913 914 mmio_clrsetbits_32(rcc + RCC_BDCR, 915 RCC_BDCR_LSEDRV_MASK, 916 value << RCC_BDCR_LSEDRV_SHIFT); 917 } 918 919 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); 920 } 921 922 static void stm32mp1_lse_wait(uint32_t rcc) 923 { 924 if (stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 925 VERBOSE("%s: failed\n", __func__); 926 } 927 } 928 929 static void stm32mp1_lsi_set(uint32_t rcc, int enable) 930 { 931 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); 932 if (stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 933 0) { 934 VERBOSE("%s: failed\n", __func__); 935 } 936 } 937 938 static void stm32mp1_hse_enable(uint32_t rcc, bool bypass, bool css) 939 { 940 if (bypass) { 941 mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP); 942 } 943 944 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); 945 if (stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 946 0) { 947 VERBOSE("%s: failed\n", __func__); 948 } 949 950 if (css) { 951 mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); 952 } 953 } 954 955 static void stm32mp1_csi_set(uint32_t rcc, int enable) 956 { 957 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); 958 if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 959 0) { 960 VERBOSE("%s: failed\n", __func__); 961 } 962 } 963 964 static void stm32mp1_hsi_set(uint32_t rcc, int enable) 965 { 966 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); 967 if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 968 0) { 969 VERBOSE("%s: failed\n", __func__); 970 } 971 } 972 973 static int stm32mp1_set_hsidiv(uint32_t rcc, uint8_t hsidiv) 974 { 975 unsigned long start; 976 uint32_t address = rcc + RCC_OCRDYR; 977 978 mmio_clrsetbits_32(rcc + RCC_HSICFGR, 979 RCC_HSICFGR_HSIDIV_MASK, 980 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 981 982 start = get_timer(0); 983 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 984 if (get_timer(start) > HSIDIV_TIMEOUT) { 985 ERROR("HSIDIV failed @ 0x%x: 0x%x\n", 986 address, mmio_read_32(address)); 987 return -ETIMEDOUT; 988 } 989 } 990 991 return 0; 992 } 993 994 static int stm32mp1_hsidiv(uint32_t rcc, unsigned long hsifreq) 995 { 996 uint8_t hsidiv; 997 uint32_t hsidivfreq = MAX_HSI_HZ; 998 999 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1000 if (hsidivfreq == hsifreq) { 1001 break; 1002 } 1003 1004 hsidivfreq /= 2U; 1005 } 1006 1007 if (hsidiv == 4U) { 1008 ERROR("Invalid clk-hsi frequency\n"); 1009 return -1; 1010 } 1011 1012 if (hsidiv != 0U) { 1013 return stm32mp1_set_hsidiv(rcc, hsidiv); 1014 } 1015 1016 return 0; 1017 } 1018 1019 static void stm32mp1_pll_start(struct stm32mp1_clk_priv *priv, 1020 enum stm32mp1_pll_id pll_id) 1021 { 1022 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1023 1024 mmio_write_32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_PLLON); 1025 } 1026 1027 static int stm32mp1_pll_output(struct stm32mp1_clk_priv *priv, 1028 enum stm32mp1_pll_id pll_id, uint32_t output) 1029 { 1030 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1031 uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; 1032 unsigned long start; 1033 1034 start = get_timer(0); 1035 /* Wait PLL lock */ 1036 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1037 if (get_timer(start) > PLLRDY_TIMEOUT) { 1038 ERROR("PLL%d start failed @ 0x%x: 0x%x\n", 1039 pll_id, pllxcr, mmio_read_32(pllxcr)); 1040 return -ETIMEDOUT; 1041 } 1042 } 1043 1044 /* Start the requested output */ 1045 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1046 1047 return 0; 1048 } 1049 1050 static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv, 1051 enum stm32mp1_pll_id pll_id) 1052 { 1053 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1054 uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; 1055 unsigned long start; 1056 1057 /* Stop all output */ 1058 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1059 RCC_PLLNCR_DIVREN); 1060 1061 /* Stop PLL */ 1062 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1063 1064 start = get_timer(0); 1065 /* Wait PLL stopped */ 1066 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1067 if (get_timer(start) > PLLRDY_TIMEOUT) { 1068 ERROR("PLL%d stop failed @ 0x%x: 0x%x\n", 1069 pll_id, pllxcr, mmio_read_32(pllxcr)); 1070 return -ETIMEDOUT; 1071 } 1072 } 1073 1074 return 0; 1075 } 1076 1077 static void stm32mp1_pll_config_output(struct stm32mp1_clk_priv *priv, 1078 enum stm32mp1_pll_id pll_id, 1079 uint32_t *pllcfg) 1080 { 1081 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1082 uint32_t rcc = priv->base; 1083 uint32_t value; 1084 1085 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1086 RCC_PLLNCFGR2_DIVP_MASK; 1087 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1088 RCC_PLLNCFGR2_DIVQ_MASK; 1089 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1090 RCC_PLLNCFGR2_DIVR_MASK; 1091 mmio_write_32(rcc + pll[pll_id].pllxcfgr2, value); 1092 } 1093 1094 static int stm32mp1_pll_config(struct stm32mp1_clk_priv *priv, 1095 enum stm32mp1_pll_id pll_id, 1096 uint32_t *pllcfg, uint32_t fracv) 1097 { 1098 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1099 uint32_t rcc = priv->base; 1100 enum stm32mp1_plltype type = pll[pll_id].plltype; 1101 unsigned long refclk; 1102 uint32_t ifrge = 0; 1103 uint32_t src, value; 1104 1105 src = mmio_read_32(priv->base + pll[pll_id].rckxselr) & 1106 RCC_SELR_REFCLK_SRC_MASK; 1107 1108 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / 1109 (pllcfg[PLLCFG_M] + 1U); 1110 1111 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1112 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1113 return -EINVAL; 1114 } 1115 1116 if ((type == PLL_800) && (refclk >= 8000000U)) { 1117 ifrge = 1U; 1118 } 1119 1120 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1121 RCC_PLLNCFGR1_DIVN_MASK; 1122 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1123 RCC_PLLNCFGR1_DIVM_MASK; 1124 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1125 RCC_PLLNCFGR1_IFRGE_MASK; 1126 mmio_write_32(rcc + pll[pll_id].pllxcfgr1, value); 1127 1128 /* Fractional configuration */ 1129 value = 0; 1130 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1131 1132 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1133 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1134 1135 value |= RCC_PLLNFRACR_FRACLE; 1136 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1137 1138 stm32mp1_pll_config_output(priv, pll_id, pllcfg); 1139 1140 return 0; 1141 } 1142 1143 static void stm32mp1_pll_csg(struct stm32mp1_clk_priv *priv, 1144 enum stm32mp1_pll_id pll_id, 1145 uint32_t *csg) 1146 { 1147 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1148 uint32_t pllxcsg = 0; 1149 1150 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1151 RCC_PLLNCSGR_MOD_PER_MASK; 1152 1153 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1154 RCC_PLLNCSGR_INC_STEP_MASK; 1155 1156 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1157 RCC_PLLNCSGR_SSCG_MODE_MASK; 1158 1159 mmio_write_32(priv->base + pll[pll_id].pllxcsgr, pllxcsg); 1160 } 1161 1162 static int stm32mp1_set_clksrc(struct stm32mp1_clk_priv *priv, 1163 unsigned int clksrc) 1164 { 1165 uint32_t address = priv->base + (clksrc >> 4); 1166 unsigned long start; 1167 1168 mmio_clrsetbits_32(address, RCC_SELR_SRC_MASK, 1169 clksrc & RCC_SELR_SRC_MASK); 1170 1171 start = get_timer(0); 1172 while ((mmio_read_32(address) & RCC_SELR_SRCRDY) == 0U) { 1173 if (get_timer(start) > CLKSRC_TIMEOUT) { 1174 ERROR("CLKSRC %x start failed @ 0x%x: 0x%x\n", 1175 clksrc, address, mmio_read_32(address)); 1176 return -ETIMEDOUT; 1177 } 1178 } 1179 1180 return 0; 1181 } 1182 1183 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uint32_t address) 1184 { 1185 unsigned long start; 1186 1187 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1188 clkdiv & RCC_DIVR_DIV_MASK); 1189 1190 start = get_timer(0); 1191 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1192 if (get_timer(start) > CLKDIV_TIMEOUT) { 1193 ERROR("CLKDIV %x start failed @ 0x%x: 0x%x\n", 1194 clkdiv, address, mmio_read_32(address)); 1195 return -ETIMEDOUT; 1196 } 1197 } 1198 1199 return 0; 1200 } 1201 1202 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, 1203 uint32_t clksrc, uint32_t clkdiv) 1204 { 1205 uint32_t address = priv->base + (clksrc >> 4); 1206 1207 /* 1208 * Binding clksrc : 1209 * bit15-4 offset 1210 * bit3: disable 1211 * bit2-0: MCOSEL[2:0] 1212 */ 1213 if ((clksrc & 0x8U) != 0U) { 1214 mmio_clrbits_32(address, RCC_MCOCFG_MCOON); 1215 } else { 1216 mmio_clrsetbits_32(address, 1217 RCC_MCOCFG_MCOSRC_MASK, 1218 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1219 mmio_clrsetbits_32(address, 1220 RCC_MCOCFG_MCODIV_MASK, 1221 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1222 mmio_setbits_32(address, RCC_MCOCFG_MCOON); 1223 } 1224 } 1225 1226 static void stm32mp1_set_rtcsrc(struct stm32mp1_clk_priv *priv, 1227 unsigned int clksrc, bool lse_css) 1228 { 1229 uint32_t address = priv->base + RCC_BDCR; 1230 1231 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1232 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1233 mmio_clrsetbits_32(address, 1234 RCC_BDCR_RTCSRC_MASK, 1235 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1236 1237 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1238 } 1239 1240 if (lse_css) { 1241 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1242 } 1243 } 1244 1245 #define CNTCVL_OFF 0x008 1246 #define CNTCVU_OFF 0x00C 1247 1248 static void stm32mp1_stgen_config(struct stm32mp1_clk_priv *priv) 1249 { 1250 uintptr_t stgen; 1251 int p; 1252 uint32_t cntfid0; 1253 unsigned long rate; 1254 1255 stgen = fdt_get_stgen_base(); 1256 1257 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1258 p = stm32mp1_clk_get_parent(priv, STGEN_K); 1259 rate = stm32mp1_clk_get(priv, p); 1260 1261 if (cntfid0 != rate) { 1262 unsigned long long counter; 1263 1264 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1265 counter = (unsigned long long) 1266 mmio_read_32(stgen + CNTCVL_OFF); 1267 counter |= ((unsigned long long) 1268 (mmio_read_32(stgen + CNTCVU_OFF))) << 32; 1269 counter = (counter * rate / cntfid0); 1270 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1271 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1272 mmio_write_32(stgen + CNTFID_OFF, rate); 1273 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1274 1275 write_cntfrq((u_register_t)rate); 1276 1277 /* Need to update timer with new frequency */ 1278 generic_delay_timer_init(); 1279 } 1280 } 1281 1282 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1283 { 1284 uintptr_t stgen; 1285 unsigned long long cnt; 1286 1287 stgen = fdt_get_stgen_base(); 1288 1289 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1290 mmio_read_32(stgen + CNTCVL_OFF); 1291 1292 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1293 1294 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1295 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1296 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1297 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1298 } 1299 1300 static void stm32mp1_pkcs_config(struct stm32mp1_clk_priv *priv, uint32_t pkcs) 1301 { 1302 uint32_t address = priv->base + ((pkcs >> 4) & 0xFFFU); 1303 uint32_t value = pkcs & 0xFU; 1304 uint32_t mask = 0xFU; 1305 1306 if ((pkcs & BIT(31)) != 0U) { 1307 mask <<= 4; 1308 value <<= 4; 1309 } 1310 1311 mmio_clrsetbits_32(address, mask, value); 1312 } 1313 1314 int stm32mp1_clk_init(void) 1315 { 1316 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1317 uint32_t rcc = priv->base; 1318 unsigned int clksrc[CLKSRC_NB]; 1319 unsigned int clkdiv[CLKDIV_NB]; 1320 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1321 int plloff[_PLL_NB]; 1322 int ret, len; 1323 enum stm32mp1_pll_id i; 1324 bool lse_css = false; 1325 const uint32_t *pkcs_cell; 1326 1327 /* Check status field to disable security */ 1328 if (!fdt_get_rcc_secure_status()) { 1329 mmio_write_32(rcc + RCC_TZCR, 0); 1330 } 1331 1332 ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc, 1333 (uint32_t)CLKSRC_NB); 1334 if (ret < 0) { 1335 return -FDT_ERR_NOTFOUND; 1336 } 1337 1338 ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv, 1339 (uint32_t)CLKDIV_NB); 1340 if (ret < 0) { 1341 return -FDT_ERR_NOTFOUND; 1342 } 1343 1344 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1345 char name[12]; 1346 1347 sprintf(name, "st,pll@%d", i); 1348 plloff[i] = fdt_rcc_subnode_offset(name); 1349 1350 if (!fdt_check_node(plloff[i])) { 1351 continue; 1352 } 1353 1354 ret = fdt_read_uint32_array(plloff[i], "cfg", 1355 pllcfg[i], (int)PLLCFG_NB); 1356 if (ret < 0) { 1357 return -FDT_ERR_NOTFOUND; 1358 } 1359 } 1360 1361 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1362 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1363 1364 /* 1365 * Switch ON oscillator found in device-tree. 1366 * Note: HSI already ON after BootROM stage. 1367 */ 1368 if (priv->osc[_LSI] != 0U) { 1369 stm32mp1_lsi_set(rcc, 1); 1370 } 1371 if (priv->osc[_LSE] != 0U) { 1372 bool bypass; 1373 uint32_t lsedrv; 1374 1375 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1376 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1377 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1378 LSEDRV_MEDIUM_HIGH); 1379 stm32mp1_lse_enable(rcc, bypass, lsedrv); 1380 } 1381 if (priv->osc[_HSE] != 0U) { 1382 bool bypass, css; 1383 1384 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1385 css = fdt_osc_read_bool(_LSE, "st,css"); 1386 stm32mp1_hse_enable(rcc, bypass, css); 1387 } 1388 /* 1389 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1390 * => switch on CSI even if node is not present in device tree 1391 */ 1392 stm32mp1_csi_set(rcc, 1); 1393 1394 /* Come back to HSI */ 1395 ret = stm32mp1_set_clksrc(priv, CLK_MPU_HSI); 1396 if (ret != 0) { 1397 return ret; 1398 } 1399 ret = stm32mp1_set_clksrc(priv, CLK_AXI_HSI); 1400 if (ret != 0) { 1401 return ret; 1402 } 1403 1404 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1405 if (i == _PLL4) 1406 continue; 1407 ret = stm32mp1_pll_stop(priv, i); 1408 if (ret != 0) { 1409 return ret; 1410 } 1411 } 1412 1413 /* Configure HSIDIV */ 1414 if (priv->osc[_HSI] != 0U) { 1415 ret = stm32mp1_hsidiv(rcc, priv->osc[_HSI]); 1416 if (ret != 0) { 1417 return ret; 1418 } 1419 stm32mp1_stgen_config(priv); 1420 } 1421 1422 /* Select DIV */ 1423 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1424 mmio_write_32(rcc + RCC_MPCKDIVR, 1425 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1426 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); 1427 if (ret != 0) { 1428 return ret; 1429 } 1430 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); 1431 if (ret != 0) { 1432 return ret; 1433 } 1434 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); 1435 if (ret != 0) { 1436 return ret; 1437 } 1438 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); 1439 if (ret != 0) { 1440 return ret; 1441 } 1442 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); 1443 if (ret != 0) { 1444 return ret; 1445 } 1446 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); 1447 if (ret != 0) { 1448 return ret; 1449 } 1450 1451 /* No ready bit for RTC */ 1452 mmio_write_32(rcc + RCC_RTCDIVR, 1453 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1454 1455 /* Configure PLLs source */ 1456 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL12]); 1457 if (ret != 0) { 1458 return ret; 1459 } 1460 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL3]); 1461 if (ret != 0) { 1462 return ret; 1463 } 1464 1465 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL4]); 1466 if (ret != 0) { 1467 return ret; 1468 } 1469 1470 /* Configure and start PLLs */ 1471 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1472 uint32_t fracv; 1473 uint32_t csg[PLLCSG_NB]; 1474 1475 if (!fdt_check_node(plloff[i])) { 1476 continue; 1477 } 1478 1479 fracv = fdt_read_uint32_default(plloff[i], "frac", 0); 1480 1481 ret = stm32mp1_pll_config(priv, i, pllcfg[i], fracv); 1482 if (ret != 0) { 1483 return ret; 1484 } 1485 ret = fdt_read_uint32_array(plloff[i], "csg", csg, 1486 (uint32_t)PLLCSG_NB); 1487 if (ret == 0) { 1488 stm32mp1_pll_csg(priv, i, csg); 1489 } else if (ret != -FDT_ERR_NOTFOUND) { 1490 return ret; 1491 } 1492 1493 stm32mp1_pll_start(priv, i); 1494 } 1495 /* Wait and start PLLs ouptut when ready */ 1496 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1497 if (!fdt_check_node(plloff[i])) { 1498 continue; 1499 } 1500 1501 ret = stm32mp1_pll_output(priv, i, pllcfg[i][PLLCFG_O]); 1502 if (ret != 0) { 1503 return ret; 1504 } 1505 } 1506 /* Wait LSE ready before to use it */ 1507 if (priv->osc[_LSE] != 0U) { 1508 stm32mp1_lse_wait(rcc); 1509 } 1510 1511 /* Configure with expected clock source */ 1512 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_MPU]); 1513 if (ret != 0) { 1514 return ret; 1515 } 1516 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_AXI]); 1517 if (ret != 0) { 1518 return ret; 1519 } 1520 stm32mp1_set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); 1521 1522 /* Configure PKCK */ 1523 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1524 if (pkcs_cell != NULL) { 1525 bool ckper_disabled = false; 1526 uint32_t j; 1527 1528 priv->pkcs_usb_value = 0; 1529 1530 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1531 uint32_t pkcs = (uint32_t)fdt32_to_cpu(pkcs_cell[j]); 1532 1533 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1534 ckper_disabled = true; 1535 continue; 1536 } 1537 stm32mp1_pkcs_config(priv, pkcs); 1538 } 1539 1540 /* 1541 * CKPER is source for some peripheral clocks 1542 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1543 * only if previous clock is still ON 1544 * => deactivated CKPER only after switching clock 1545 */ 1546 if (ckper_disabled) { 1547 stm32mp1_pkcs_config(priv, CLK_CKPER_DISABLED); 1548 } 1549 } 1550 1551 /* Switch OFF HSI if not found in device-tree */ 1552 if (priv->osc[_HSI] == 0U) { 1553 stm32mp1_hsi_set(rcc, 0); 1554 } 1555 stm32mp1_stgen_config(priv); 1556 1557 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1558 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, 1559 RCC_DDRITFCR_DDRCKMOD_MASK, 1560 RCC_DDRITFCR_DDRCKMOD_SSR << 1561 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1562 1563 return 0; 1564 } 1565 1566 static void stm32mp1_osc_clk_init(const char *name, 1567 struct stm32mp1_clk_priv *priv, 1568 enum stm32mp_osc_id index) 1569 { 1570 uint32_t frequency; 1571 1572 priv->osc[index] = 0; 1573 1574 if (fdt_osc_read_freq(name, &frequency) != 0) { 1575 ERROR("%s frequency request failed\n", name); 1576 panic(); 1577 } else { 1578 priv->osc[index] = frequency; 1579 } 1580 } 1581 1582 static void stm32mp1_osc_init(void) 1583 { 1584 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1585 enum stm32mp_osc_id i; 1586 1587 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 1588 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], priv, i); 1589 } 1590 } 1591 1592 int stm32mp1_clk_probe(void) 1593 { 1594 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1595 1596 priv->base = fdt_rcc_read_addr(); 1597 if (priv->base == 0U) { 1598 return -EINVAL; 1599 } 1600 1601 priv->data = &stm32mp1_data; 1602 1603 if ((priv->data->gate == NULL) || (priv->data->sel == NULL) || 1604 (priv->data->pll == NULL)) { 1605 return -EINVAL; 1606 } 1607 1608 stm32mp1_osc_init(); 1609 1610 return 0; 1611 } 1612